cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / lenovo / t400 / devicetree.cb
blob259c3e1b2129f1f9c75e6b16cac00b908c74a8c0
1 chip northbridge/intel/gm45
2 # IGD Displays
3 register "gfx" = "GMA_STATIC_DISPLAYS(1)"
5 register "gpu_panel_power_up_delay" = "250" # T1+T2: 25ms
6 register "gpu_panel_power_down_delay" = "250" # T3: 25ms
7 register "gpu_panel_power_backlight_on_delay" = "2500" # T5: 250ms
8 register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms
9 register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms
11 register "slfm" = "1"
13 device cpu_cluster 0 on ops gm45_cpu_bus_ops end
15 register "pci_mmio_size" = "2048"
17 device domain 0 on
18 ops gm45_pci_domain_ops
19 device pci 00.0 on
20 subsystemid 0x17aa 0x20e0
21 end # host bridge
22 device pci 01.0 on end # PCIe Bridge for discrete graphics
23 device pci 02.0 on # VGA
24 subsystemid 0x17aa 0x20e4
25 end
26 device pci 02.1 on
27 subsystemid 0x17aa 0x20e4
28 end # Display
29 device pci 03.0 on
30 subsystemid 0x17aa 0x20e6
31 end # ME
32 device pci 03.1 off end # ME
33 device pci 03.2 off end # ME
34 device pci 03.3 off end # ME
35 chip southbridge/intel/i82801ix
36 register "pirqa_routing" = "0x0b"
37 register "pirqb_routing" = "0x0b"
38 register "pirqc_routing" = "0x0b"
39 register "pirqd_routing" = "0x0b"
40 register "pirqe_routing" = "0x80"
41 register "pirqf_routing" = "0x80"
42 register "pirqg_routing" = "0x80"
43 register "pirqh_routing" = "0x80"
45 register "gpi8_routing" = "2"
46 register "gpe0_en" = "0x01000000"
47 register "gpi1_routing" = "2"
49 # Set AHCI mode, enable ports 1 and 2.
50 register "sata_port_map" = "0x03"
51 register "sata_clock_request" = "0"
52 register "sata_traffic_monitor" = "0"
54 # Set c-state support
55 register "c4onc3_enable" = "1"
56 register "c5_enable" = "1"
57 register "c6_enable" = "1"
59 # Set thermal throttling to 75%.
60 register "throttle_duty" = "THTL_75_0"
62 # Enable PCIe ports 1,2,4 as slots (Mini * PCIe).
63 register "pcie_slot_implemented" = "0xb"
64 # Set power limits to 10 * 10^0 watts.
65 # Maybe we should set less for Mini PCIe.
66 register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }"
67 register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
68 register "gen1_dec" = "0x007c1601"
69 register "gen2_dec" = "0x000c15e1"
70 register "gen3_dec" = "0x001c1681"
72 device pci 19.0 on end # LAN
73 device pci 1a.0 on # UHCI
74 subsystemid 0x17aa 0x20f0
75 end
76 device pci 1a.1 on # UHCI
77 subsystemid 0x17aa 0x20f0
78 end
79 device pci 1a.2 on # UHCI
80 subsystemid 0x17aa 0x20f0
81 end
82 device pci 1a.7 on # EHCI
83 subsystemid 0x17aa 0x20f1
84 end
85 device pci 1b.0 on # HD Audio
86 subsystemid 0x17aa 0x20f2
87 end
88 device pci 1c.0 on # PCIe Port #1
89 subsystemid 0x17aa 0x20f3 # WWAN
90 end
91 device pci 1c.1 on
92 subsystemid 0x17aa 0x20f3 # WLAN
93 end # PCIe Port #2
94 device pci 1c.2 on
95 subsystemid 0x17aa 0x20f3 # UWB
96 end # PCIe Port #3
97 device pci 1c.3 on
98 subsystemid 0x17aa 0x20f3 # Expresscard
99 smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
100 end # PCIe Port #4
101 device pci 1c.4 off end # PCIe Port #5
102 device pci 1c.5 off end # PCIe Port #6
103 device pci 1d.0 on # UHCI
104 subsystemid 0x17aa 0x20f0
106 device pci 1d.1 on # UHCI
107 subsystemid 0x17aa 0x20f0
109 device pci 1d.2 on # UHCI
110 subsystemid 0x17aa 0x20f0
112 device pci 1d.7 on # EHCI
113 subsystemid 0x17aa 0x20f1
115 device pci 1e.0 on # PCI
116 subsystemid 0x17aa 0x20f4
118 device pci 1f.0 on # LPC bridge
119 subsystemid 0x17aa 0x20f5
121 chip ec/lenovo/pmh7
122 device pnp ff.1 on end # dummy
123 register "backlight_enable" = "true"
124 register "dock_event_enable" = "true"
127 chip ec/lenovo/h8
128 device pnp ff.2 on # dummy
129 io 0x60 = 0x62
130 io 0x62 = 0x66
131 io 0x64 = 0x1600
132 io 0x66 = 0x1604
135 register "config0" = "0xa6"
136 register "config1" = "0x04"
137 register "config2" = "0xa0"
138 register "config3" = "0x01"
140 register "beepmask0" = "0xfe"
141 register "beepmask1" = "0x96"
142 register "has_power_management_beeps" = "1"
143 register "has_uwb" = "1"
145 register "event2_enable" = "0xff"
146 register "event3_enable" = "0xff"
147 register "event4_enable" = "0xf4"
148 register "event5_enable" = "0x3c"
149 register "event6_enable" = "0x80"
150 register "event7_enable" = "0x01"
151 register "event8_enable" = "0x01"
152 register "event9_enable" = "0xff"
153 register "eventa_enable" = "0xff"
154 register "eventb_enable" = "0xff"
155 register "eventc_enable" = "0xff"
156 register "eventd_enable" = "0xff"
158 register "has_bdc_detection" = "1"
159 register "bdc_gpio_num" = "48"
160 register "bdc_gpio_lvl" = "0"
163 chip superio/nsc/pc87382
164 device pnp 164e.2 off end # IR
165 device pnp 164e.3 off end # Serial Port
166 device pnp 164e.7 on # GPIO
167 io 0x60 = 0x1680
169 device pnp 164e.19 on # DLPC
170 io 0x60 = 0x164c
174 chip superio/nsc/pc87384
175 device pnp 2e.1 on # Parallel Port
176 io 0x60 = 0x3bc
177 irq 0x70 = 7
179 device pnp 2e.2 off end # Serial Port / IR
180 device pnp 2e.3 on # Serial Port
181 io 0x60 = 0x3f8
182 irq 0x70 = 4
184 device pnp 2e.7 on # GPIO
185 io 0x60 = 0x1620
189 device pci 1f.2 on # SATA/IDE 1
190 subsystemid 0x17aa 0x20f8
192 device pci 1f.3 on end # SMBus
193 device pci 1f.5 off end # SATA/IDE 2
194 device pci 1f.6 off end # Thermal