3 This page describes how to run coreboot on the [ASUS P8H61-M LX].
8 +---------------------+------------+
10 +=====================+============+
11 | Socketed flash | yes |
12 +---------------------+------------+
14 +---------------------+------------+
16 +---------------------+------------+
18 +---------------------+------------+
19 | Write protection | no |
20 +---------------------+------------+
21 | Dual BIOS feature | no |
22 +---------------------+------------+
23 | Internal flashing | yes |
24 +---------------------+------------+
27 ### Internal programming
29 The main SPI flash can be accessed using [flashrom]. By default, only
30 the BIOS region of the flash is writable. If you wish to change any
31 other region (Management Engine or flash descriptor), then an external
32 programmer is required.
34 The following command may be used to flash coreboot:
37 $ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
40 The use of `--noverify-all` is required since the Management Engine
41 region is not readable even by the host.
45 - S3 suspend/resume does not work. This is the case for both coreboot
46 and the vendor firmware, tested with Linux 4.9, Linux 4.17, and
47 OpenBSD 6.3. Interestingly, it is possible to resume from S3 with
48 Linux, but _only_ if the resume is started immediately after the
51 - There is no automatic, OS-independent fan control. This is because
52 the Super I/O hardware monitor can only obtain valid CPU temperature
53 readings from the PECI agent, whose complete initialisation is not
54 publicly documented. The `coretemp` driver can still be used for
55 accurate CPU temperature readings.
74 - hardware monitor (see [Known issues](#known-issues) for caveats)
77 - native raminit (2 x 2GB, DDR3-1333)
78 - native graphics init (libgfxinit)
79 - flashrom under the vendor firmware
80 - flashrom under coreboot
82 - Using `me_cleaner` (add `-S --whitelist EFFS,FCRS` if not using
83 `me_cleaner` as part of the coreboot build process).
88 +------------------+--------------------------------------------------+
89 | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
90 +------------------+--------------------------------------------------+
91 | Southbridge | bd82x6x |
92 +------------------+--------------------------------------------------+
94 +------------------+--------------------------------------------------+
95 | Super I/O | Nuvoton NCT6776 |
96 +------------------+--------------------------------------------------+
98 +------------------+--------------------------------------------------+
99 | Coprocessor | Intel Management Engine |
100 +------------------+--------------------------------------------------+
106 - [Flash chip datasheet][W25Q32BV]
108 [ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/
109 [W25Q32BV]: https://web.archive.org/web/20211002141814/https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
110 [flashrom]: https://flashrom.org/Flashrom
111 [Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip