3 This page describes how to run coreboot on the [ASUS P8Z77-V].
8 +---------------------+----------------+
10 +=====================+================+
11 | Socketed flash | yes |
12 +---------------------+----------------+
13 | Model | W25Q64FVA1Q |
14 +---------------------+----------------+
16 +---------------------+----------------+
18 +---------------------+----------------+
19 | Write protection | yes |
20 +---------------------+----------------+
21 | Dual BIOS feature | no |
22 +---------------------+----------------+
23 | Internal flashing | no |
24 +---------------------+----------------+
27 The flash IC is located between the black and white PCI Express x16 slots (circled):
32 The main SPI flash cannot be written because the vendor firmware disables BIOSWE
33 and enables BLE/SMM_BWP flags in BIOS_CNTL for their latest BIOSes. An external
34 programmer is required. You must flash standalone, flashing in-circuit doesn't
35 work. The flash chip is socketed, so it's easy to remove and reflash.
39 - PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.28
40 - Integrated Ethernet NIC
42 - USB2 on rear and front panel connectors
43 - USB3 (Z77's and ASMedia's works)
44 - Integrated SATA of Z77
45 - Integrated SATA of ASM1061 (works under GNU/Linux but not under SeaBIOS)
46 - CPU Temp sensors (tested PSensor on GNU/Linux)
47 - TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12)
49 - Integrated graphics with libgfxinit (VGA/DVI-D/HDMI tested and working)
50 - PCIe in PCIe-16x/8x slots (tested using an S3 Matrix GPU)
51 - Debug output from serial port
52 - Atheros AR9485 half-height mini PCIe WNIC adapted with Wi-Fi Go! Adapter
53 - Default PCIe config (PCIEX_16_3 as 1x, PCIe Port 4 to ASM1061 SATA, see below
54 for other potential options)
64 - PCIEX_1_2 (expected under default PCIe config)
65 - Other PCIe configs (see below)
68 On Asus vendor firmware, other than the default config already supported here,
69 there remain another two configs: "PCIEX_16_3 as x4, with PCIEX_1_1, PCIEX_1_2
70 and onboard ASM1061 disabled" and "PCIEX_16_3 as x1, but PCIe Port 4 to PCIEX_1_2,
71 with onboard ASM1061 disabled".
73 Configuring PCIEX_16_3 as x4 needs to program 0x3 to the LSB of PCHSTRP9, but
74 also needs to configure GPIOs in the Super I/O chip different than the default
75 config in this board's override tree.
77 Configuring PCIe Port 4 to PCIEX_1_2 needs to configure GPIOs in the Super I/O
78 chip differently than the default config.
80 I have tried a lot, but sadly I am unable to produce the same result as the vendor
84 Asus Wi-Fi Go! has several versions. P8Z77-V has the earliest version.
85 See [Asus Wi-Fi Go! v1].
90 +------------------+--------------------------------------------------+
91 | Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
92 +------------------+--------------------------------------------------+
93 | Southbridge | bd82x6x |
94 +------------------+--------------------------------------------------+
96 +------------------+--------------------------------------------------+
97 | Super I/O | Nuvoton NCT6779D |
98 +------------------+--------------------------------------------------+
100 +------------------+--------------------------------------------------+
101 | Coprocessor | Intel Management Engine |
102 +------------------+--------------------------------------------------+
107 - [Flash chip datasheet][W25Q64FVA1Q]
109 [ASUS P8Z77-V]: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/
110 [W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
111 [flashrom]: https://flashrom.org/Flashrom
112 [Asus Wi-Fi Go! v1]: ./wifigo_v1.md