1 # RAM initialization feature matrix
7 * Native Raminit is working for most frequencies on most boards.
8 * There might be errors to fix.
9 * Position in romstage doesn't matter.
11 * Closed Source (aka blob)
13 * Needs to be placed at fixed offset in romstage.
15 ## Native raminit implemented features
18 +---------------------------+----------------------+-------------+---------+---------------------+
19 | Option | Supported | Implemented | Working | Comments |
20 +===========================+======================+=============+=========+=====================+
21 | **Supported channels** |
22 +---------------------------+----------------------+-------------+---------+---------------------+
23 | single and dual channel | yes | yes | yes | |
24 +---------------------------+----------------------+-------------+---------+---------------------+
25 | Up to 4 slots | yes | yes | yes | |
26 +---------------------------+----------------------+-------------+---------+---------------------+
27 | Up to 4 ranks per channel | yes | yes | yes | |
28 +---------------------------+----------------------+-------------+---------+---------------------+
29 | **Supported frequencies** |
30 +---------------------------+----------------------+-------------+---------+---------------------+
31 | DDR3-1066 (533MHz) | yes | yes | yes | |
32 +---------------------------+----------------------+-------------+---------+---------------------+
33 | DDR3-1600 (800MHz) | yes | yes | yes | |
34 +---------------------------+----------------------+-------------+---------+---------------------+
35 | DDR3-1866 (933MHz) | yes | yes | yes | |
36 +---------------------------+----------------------+-------------+---------+---------------------+
37 | DDR3-2133 (1066MHz) | yes | yes | yes | |
38 +---------------------------+----------------------+-------------+---------+---------------------+
39 | DDR3-1400 (700MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |
40 +---------------------------+----------------------+-------------+---------+---------------------+
41 | DDR3-1800 (900MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |
42 +---------------------------+----------------------+-------------+---------+---------------------+
43 | DDR3-2000 (1000MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |
44 +---------------------------+----------------------+-------------+---------+---------------------+
45 | DDR3-2200 (1100MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |
46 +---------------------------+----------------------+-------------+---------+---------------------+
47 | DDR3-2400 (1200MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |
48 +---------------------------+----------------------+-------------+---------+---------------------+
49 | DDR3-1800 (900MHz) | yes (IvyBridge only) | yes | yes | Since coreboot 4.6 |
50 +---------------------------+----------------------+-------------+---------+---------------------+
51 | **Supported CAS latencies** |
52 +---------------------------+----------------------+-------------+---------+---------------------+
53 | CL6 | yes | yes | ? | |
54 +---------------------------+----------------------+-------------+---------+---------------------+
55 | CL7 | yes | yes | ? | |
56 +---------------------------+----------------------+-------------+---------+---------------------+
57 | CL8 | yes | yes | ? | |
58 +---------------------------+----------------------+-------------+---------+---------------------+
59 | CL9 | yes | yes | ? | |
60 +---------------------------+----------------------+-------------+---------+---------------------+
61 | CL10 | yes | yes | yes | |
62 +---------------------------+----------------------+-------------+---------+---------------------+
63 | CL11 | yes | yes | yes | |
64 +---------------------------+----------------------+-------------+---------+---------------------+
65 | CL12 | yes | yes | ? | Since coreboot 4.6 |
66 +---------------------------+----------------------+-------------+---------+---------------------+
67 | CL13 | yes | yes | yes | Since coreboot 4.6 |
68 +---------------------------+----------------------+-------------+---------+---------------------+
69 | CL14 | yes | yes | ? | Since coreboot 4.6 |
70 +---------------------------+----------------------+-------------+---------+---------------------+
71 | CL15 | yes | yes | ? | Since coreboot 4.6 |
72 +---------------------------+----------------------+-------------+---------+---------------------+
73 | **MRC cache (stored timings of last training)** |
74 +---------------------------+----------------------+-------------+---------+---------------------+
75 | S3 | yes | yes | yes | |
76 +---------------------------+----------------------+-------------+---------+---------------------+
77 | normal boot | yes | yes | yes | reset on CRC16 diff |
78 +---------------------------+----------------------+-------------+---------+---------------------+
80 +---------------------------+----------------------+-------------+---------+---------------------+
81 | XMP Profile 1 | yes | yes | yes | only 1.5 V profiles |
82 +---------------------------+----------------------+-------------+---------+---------------------+
83 | XMP Profile 2 | yes | yes | no | not activated |
84 +---------------------------+----------------------+-------------+---------+---------------------+
86 +---------------------------+----------------------+-------------+---------+---------------------+
87 | ECC | yes | yes | yes | Since coreboot 4.13 |
88 +---------------------------+----------------------+-------------+---------+---------------------+