Documentation/northbridge/intel/sandybridge/nri_freq.md

   1 # Frequency selection
   2
   3 ## Introduction
   4 This chapter explains the frequency selection done on Sandy Bridge and Ivy
   5 Bridge memory initialization.
   6
   7 ## Definitions
   8 ```{eval-rst}
   9 +---------+-------------------------------------------------------------------+------------+--------------+
  10 | Symbol  | Description                                                       | Units      | Valid region |
  11 +=========+===================================================================+============+==============+
  12 | SCK     | DRAM system clock cycle time                                      | s          |              |
  13 +---------+-------------------------------------------------------------------+------------+--------------+
  14 | tCK     | DRAM system clock cycle time                                      | 1/256th ns |              |
  15 +---------+-------------------------------------------------------------------+------------+--------------+
  16 | DCK     | Data clock cycle time: The time between two SCK clock edges       | s          |              |
  17 +---------+-------------------------------------------------------------------+------------+--------------+
  18 | SPD     | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes      |              |
  19 +---------+-------------------------------------------------------------------+------------+--------------+
  20 | REFCK   | Reference clock, either 100 or 133                                | MHz        | 100, 133     |
  21 +---------+-------------------------------------------------------------------+------------+--------------+
  22 | MULT    | DRAM PLL multiplier                                               |            | [3-12]       |
  23 +---------+-------------------------------------------------------------------+------------+--------------+
  24 | XMP     | Extreme Memory Profiles                                           |            |              |
  25 +---------+-------------------------------------------------------------------+------------+--------------+
  26 ```
  27 ## SPD
  28 The [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
  29 located on every DIMM is factory program with various timings. One of them
  30 specifies the maximum clock frequency the DIMM should be used with. The
  31 operating frequency is stores as fixed point value (tCK), rounded to the next
  32 smallest supported operating frequency. Some
  33 [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
  34 contains additional and optional
  35 [XMP](https://de.wikipedia.org/wiki/Extreme_Memory_Profile "Extreme Memory Profile")
  36 data, that stores so called "performance" modes, that advertises higher clock
  37 frequencies.
  38
  39 ## XMP profiles
  40 At time of writing coreboot's raminit is able to parse XMP profile 1 and 2.
  41 Only **XMP profile 1** is being used in case it advertises:
  42 * 1.5V operating voltage
  43 * The channel's installed DIMM count doesn't exceed the XMP coded limit
  44
  45 In case the XMP profile doesn't fulfill those limits, the regular SPD will be
  46 used.
  47 > **Note:** XMP Profiles are supported since coreboot 4.4.
  48
  49 It is possible to ignore the max DIMM count limit set by XMP profiles.
  50 By activating Kconfig option `NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS` it is
  51 possible to install two DIMMs per channel, even if XMP tells you not to do.
  52
  53 > **Note:** Ignoring XMP Profiles limit is supported since coreboot 4.7.
  54
  55 ## Soft fuses
  56 Every board manufacturer does program "soft" fuses to indicate the maximum
  57 DRAM frequency supported. However, those fuses don't set a limit in hardware
  58 and thus are called "soft" fuses, as it is possible to ignore them.
  59
  60 > **Note:** Ignoring the fuses might cause system instability !
  61
  62 On Sandy Bridge *CAPID0_A* is being read, and on Ivy Bridge *CAPID0_B* is being
  63 read. coreboot reads those registers and honors the limit in case the Kconfig
  64 option `CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES` wasn't set.
  65 Power users that want to let their RAM run at DRAM's "stock" frequency need to
  66 enable the Kconfig symbol.
  67
  68 It is possible to override the soft fuses limit by using a board-specific
  69 [devicetree](#devicetree) setting.
  70
  71 > **Note:** Ignoring max mem freq. fuses is supported since coreboot 4.7.
  72
  73 ## Hard fuses
  74 "Hard" fuses are programmed by Intel and limit the maximum frequency that can
  75 be used on a given CPU/board/chipset. At time of writing there's no register
  76 to read this limit, before trying to set a given DRAM frequency. The memory PLL
  77 won't lock, indicating that the chosen memory multiplier isn't available. In
  78 this case coreboot tries the next smaller memory multiplier until the PLL will
  79 lock.
  80
  81 ## Devicetree
  82 The devicetree register `max_mem_clock_mhz` overrides the "soft" fuses set
  83 by the board manufacturer.
  84
  85 By using this register it's possible to force a minimum operating frequency.
  86
  87 ## Reference clock
  88 While Sandy Bridge supports 133 MHz reference clock (REFCK), Ivy Bridge also
  89 supports 100 MHz reference clock. The reference clock is multiplied by the DRAM
  90 multiplier to select the DRAM frequency (SCK) by the following formula:
  91
  92  REFCK * MULT = 1 / DCK
  93
  94 > **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
  95
  96 ## Sandy Bridge's supported frequencies
  97 ```{eval-rst}
  98 +------------+-----------+------------------+-------------------------+---------------+
  99 | SCK [Mhz]  | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment       |
 100 +============+===========+==================+=========================+===============+
 101 | 400        | DDR3-800  | 3                | 133 MHz                 |               |
 102 +------------+-----------+------------------+-------------------------+---------------+
 103 | 533        | DDR3-1066 | 4                | 133 MHz                 |               |
 104 +------------+-----------+------------------+-------------------------+---------------+
 105 | 666        | DDR3-1333 | 5                | 133 MHz                 |               |
 106 +------------+-----------+------------------+-------------------------+---------------+
 107 | 800        | DDR3-1600 | 6                | 133 MHz                 |               |
 108 +------------+-----------+------------------+-------------------------+---------------+
 109 | 933        | DDR3-1866 | 7                | 133 MHz                 |               |
 110 +------------+-----------+------------------+-------------------------+---------------+
 111 | 1066       | DDR3-2166 | 8                | 133 MHz                 |               |
 112 +------------+-----------+------------------+-------------------------+---------------+
 113 ```
 114
 115 ## Ivy Bridge's supported frequencies
 116 ```{eval-rst}
 117 +------------+-----------+------------------+-------------------------+---------------+
 118 | SCK [Mhz]  | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment       |
 119 +============+===========+==================+=========================+===============+
 120 | 400        | DDR3-800  | 3                | 133 MHz                 |               |
 121 +------------+-----------+------------------+-------------------------+---------------+
 122 | 533        | DDR3-1066 | 4                | 133 MHz                 |               |
 123 +------------+-----------+------------------+-------------------------+---------------+
 124 | 666        | DDR3-1333 | 5                | 133 MHz                 |               |
 125 +------------+-----------+------------------+-------------------------+---------------+
 126 | 800        | DDR3-1600 | 6                | 133 MHz                 |               |
 127 +------------+-----------+------------------+-------------------------+---------------+
 128 | 933        | DDR3-1866 | 7                | 133 MHz                 |               |
 129 +------------+-----------+------------------+-------------------------+---------------+
 130 | 1066       | DDR3-2166 | 8                | 133 MHz                 |               |
 131 +------------+-----------+------------------+-------------------------+---------------+
 132 | 700        | DDR3-1400 | 7                | 100 MHz                 | '1            |
 133 +------------+-----------+------------------+-------------------------+---------------+
 134 | 800        | DDR3-1600 | 8                | 100 MHz                 | '1            |
 135 +------------+-----------+------------------+-------------------------+---------------+
 136 | 900        | DDR3-1800 | 9                | 100 MHz                 | '1            |
 137 +------------+-----------+------------------+-------------------------+---------------+
 138 | 1000       | DDR3-2000 | 10               | 100 MHz                 | '1            |
 139 +------------+-----------+------------------+-------------------------+---------------+
 140 | 1100       | DDR3-2200 | 11               | 100 MHz                 | '1            |
 141 +------------+-----------+------------------+-------------------------+---------------+
 142 | 1200       | DDR3-2400 | 12               | 100 MHz                 | '1            |
 143 +------------+-----------+------------------+-------------------------+---------------+
 144 ```
 145 > '1: since coreboot 4.6
 146
 147 ## Multiplier selection
 148 coreboot selects the maximum frequency to operate at by the following formula:
 149 ```
 150 if devicetree's max_mem_clock_mhz > 0:
 151      freq_max := max_mem_clock_mhz
 152 else:
 153      freq_max := soft_fuse_max_mhz
 154
 155 for i in SPDs:
 156      freq_max := MIN(freq_max, ddr_spd_max_mhz[i])
 157 ```
 158
 159 As you can see, by using DIMMs with different maximum DRAM frequencies, the
 160 slowest DIMMs' frequency will be selected, to prevent over-clocking it.
 161
 162 The selected frequency gives the PLL multiplier to operate at. In case the PLL
 163 locks (see Take me to [Hard fuses](#hard-fuses)) the frequency will be used for
 164 all DIMMs. At this point it's not possible to change the multiplier again,
 165 until the system has been powered off. In case the PLL doesn't lock, the next
 166 smaller multiplier will be used until a working multiplier will be found.