mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / configs / builder / config.intel.crb.ac
blob73e2eea06f312ff64d564d245f74fdbb3d980c78
1 # Intel ArcherCity CRB is a dual socket CRB based on Intel
2 # Sapphire Rapids Scalable Processor (SPR-SP) chipset.
4 # Type this in coreboot root directory to get a working .config:
5 #   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.ac
7 CONFIG_VENDOR_INTEL=y
8 CONFIG_BOARD_INTEL_ARCHERCITY_CRB=y
9 CONFIG_HAVE_IFD_BIN=y
10 CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
11 CONFIG_PAYLOAD_LINUX=y
12 CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage"
13 CONFIG_HAVE_ME_BIN=y
14 CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
15 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
16 CONFIG_ADD_FSP_BINARIES=y
17 CONFIG_FSP_T_FILE="site-local/archercity/Server_T.fd"
18 CONFIG_FSP_M_FILE="site-local/archercity/Server_M.fd"
19 CONFIG_FSP_S_FILE="site-local/archercity/Server_S.fd"
20 CONFIG_IFD_BIN_PATH="site-local/archercity/descriptor.bin"
21 CONFIG_ME_BIN_PATH="site-local/archercity/me.bin"
22 CONFIG_CPU_UCODE_BINARIES="site-local/archercity/mbf806f8.mcb"
23 CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
24 CONFIG_NO_GFX_INIT=y