mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / console / init.c
blob3b89326c7fb6084639e1c4b68034b5490e75cca9
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <commonlib/helpers.h>
4 #include <console/cbmem_console.h>
5 #include <console/console.h>
6 #include <console/uart.h>
7 #include <console/streams.h>
8 #include <device/pci.h>
9 #include <option.h>
10 #include <version.h>
12 #define FIRST_CONSOLE (ENV_BOOTBLOCK || (CONFIG(NO_BOOTBLOCK_CONSOLE) && ENV_SEPARATE_ROMSTAGE))
14 static int console_inited;
15 static int console_loglevel;
17 int get_log_level(void)
19 if (console_inited == 0)
20 return -1;
22 return console_loglevel;
25 static void init_log_level(void)
27 console_loglevel = get_console_loglevel();
29 if (!FIRST_CONSOLE)
30 console_loglevel = get_uint_option("debug_level", console_loglevel);
33 int console_log_level(int msg_level)
35 int log_level = get_log_level();
37 if (log_level < 0)
38 return CONSOLE_LOG_NONE;
40 if (msg_level <= log_level)
41 return CONSOLE_LOG_ALL;
43 if (CONFIG(CONSOLE_CBMEM) && (msg_level <= BIOS_DEBUG))
44 return CONSOLE_LOG_FAST;
46 return 0;
49 void console_init(void)
51 init_log_level();
53 if (CONFIG(DEBUG_CONSOLE_INIT))
54 console_inited = 1;
56 if (CONFIG(EARLY_PCI_BRIDGE) && (ENV_BOOTBLOCK || ENV_SEPARATE_ROMSTAGE))
57 pci_early_bridge_init();
59 console_hw_init();
61 console_inited = 1;
63 if (ENV_BOOTBLOCK && CONFIG(CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS))
64 cbmem_dump_console();
66 printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_ARCH " " ENV_STRING " starting (log level: %i)...\n",
67 coreboot_version, coreboot_extra_version, coreboot_build, get_log_level());