mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / acer / aspire_vn7_572g / bootblock.c
blobce150fdce7f6d36f0cba1f5be7ccf2dcc586f0c3
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <bootblock_common.h>
4 #include <console/console.h>
5 #include <delay.h>
6 #include <gpio.h>
7 #include "include/ec.h"
8 #include "include/gpio.h"
10 #define ADC_3V_10BIT_GRANULARITY_MAX (3005 / 1023)
11 #define PCB_VER_AD 1
12 #define MODEL_ID_AD 3
14 #define DGPU_PRESENT GPP_A20 /* Active low */
15 #define DGPU_HOLD_RST GPP_B4 /* Active low */
16 #define DGPU_PWR_EN GPP_B21 /* Active low */
18 /* TODO/NB: Detection is still unreliable. Is a wait required? */
19 static void board_detect(void)
21 printk(BIOS_DEBUG, "Mainboard: Detecting board SKU\n");
23 uint16_t data_buffer = read_ec_adc_converter(MODEL_ID_AD);
24 printk(BIOS_DEBUG, "BoardId (raw) = 0x%x\n", data_buffer);
25 printk(BIOS_DEBUG, "BoardId: ");
26 /* Board by max millivoltage range (of 10-bit, 3.005 V ADC) */
27 if (data_buffer <= (1374 / ADC_3V_10BIT_GRANULARITY_MAX)) {
28 printk(BIOS_ERR, "Reserved?\n");
29 } else if (data_buffer <= (2017 / ADC_3V_10BIT_GRANULARITY_MAX)) {
30 printk(BIOS_DEBUG, "Aspire VN7-792G (Newgate-SLS_dGPU)\n");
31 printk(BIOS_CRIT, "WARNING: This board is unsupported!\n");
32 printk(BIOS_CRIT, "Damage may result from programming incorrect GPIO table!\n");
33 } else if (data_buffer <= (2259 / ADC_3V_10BIT_GRANULARITY_MAX)) {
34 printk(BIOS_DEBUG, "Aspire VN7-592G (Rayleigh-SLS_960M)\n");
35 printk(BIOS_CRIT, "WARNING: This board is unsupported!\n");
36 printk(BIOS_CRIT, "Damage may result from programming incorrect GPIO table!\n");
37 } else {
38 printk(BIOS_DEBUG, "Aspire VN7-572G (Rayleigh-SL_dGPU)\n");
41 data_buffer = read_ec_adc_converter(PCB_VER_AD);
42 printk(BIOS_DEBUG, "PCB version (raw) = 0x%x\n", data_buffer);
43 printk(BIOS_DEBUG, "PCB version: ");
44 /* PCB by max millivoltage range (of 10-bit, 3.005 V ADC) */
45 if (data_buffer <= (2017 / ADC_3V_10BIT_GRANULARITY_MAX)) {
46 printk(BIOS_ERR, "Reserved?\n");
47 } else if (data_buffer <= (2259 / ADC_3V_10BIT_GRANULARITY_MAX)) {
48 printk(BIOS_DEBUG, "-1\n");
49 } else if (data_buffer <= (2493 / ADC_3V_10BIT_GRANULARITY_MAX)) {
50 printk(BIOS_DEBUG, "SC\n");
51 } else if (data_buffer <= (2759 / ADC_3V_10BIT_GRANULARITY_MAX)) {
52 printk(BIOS_DEBUG, "SB\n");
53 } else {
54 printk(BIOS_DEBUG, "SA\n");
58 static void dgpu_power_on(void)
60 if (!gpio_get(DGPU_PRESENT)) {
61 printk(BIOS_DEBUG, "dGPU present, enable power...\n");
62 gpio_set(DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#
63 mdelay(2);
64 gpio_set(DGPU_PWR_EN, 0); // Assert dGPU_PWR_EN#
65 mdelay(7);
66 gpio_set(DGPU_HOLD_RST, 1); // Deassert dGPU_HOLD_RST#
67 mdelay(30);
68 } else {
69 printk(BIOS_DEBUG, "dGPU not present, disable power...\n");
70 gpio_set(DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#
71 gpio_set(DGPU_PWR_EN, 1); // Deassert dGPU_PWR_EN#
75 void bootblock_mainboard_init(void)
77 /* NB: Relocated from _early_init() so that debug logging works.
78 * However, if we use this to ensure that the user flashed the correct
79 * (future) variant, this must occur before any GPIOs are programmed.
81 board_detect();
82 dgpu_power_on();
85 void bootblock_mainboard_early_init(void)
87 mainboard_config_stage_gpios();