mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / acer / aspire_vn7_572g / hda_verb.c
blob20197d1d22bbc6589c3ca2428b574c17ecfd6408
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 /* TODO: Convert to macros */
5 #include <device/azalia_device.h>
7 const u32 cim_verb_data[] = {
8 /* --- Codec #0 --- */
9 /* coreboot specific header */
10 0x10ec0255, /* Codec Vendor / Device ID: Realtek ALC255 */
11 0x10251037, /* Subsystem ID */
12 20, /* Number of jacks (NID entries) */
14 /* Codec Address: Bits 31:28 */
15 /* Node ID: Bits 27:20 */
16 /* Verb ID: Bits 19:8 / Bits 19:16 */
17 /* Payload: Bits 7:0 / Bits 15:0 */
19 /* Reset Codec */
20 AZALIA_RESET(0x1),
21 /* NOTE: Corrected the table in vendor FW, programming subsystem after reset */
22 /* HDA Codec Subsystem ID Verb Table */
23 AZALIA_SUBVENDOR(0, 0x10251037),
25 /* Pin Widget Verb Table */
26 AZALIA_PIN_CFG(0, 0x12, 0x411111c0),
27 AZALIA_PIN_CFG(0, 0x14, 0x90172120), /* Speaker */
28 AZALIA_PIN_CFG(0, 0x17, 0x40000000),
29 AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
30 AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
31 AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
32 AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
33 AZALIA_PIN_CFG(0, 0x1d, 0x40700001),
34 AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
35 AZALIA_PIN_CFG(0, 0x21, 0x02211030), /* Headphone */
38 * See data blob in "InstallPchHdaVerbTablePei" of vendor firmware
39 * (some appear in https://github.com/torvalds/linux/blob/master/sound/pci/hda/patch_realtek.c).
40 * - Largely coefficient programming (undocumented): Select coeff; write data
41 * - Also programs speaker amplifier gain
42 * - Sets speaker output
43 * NOTE: NID 0x20 holds the "Realtek Defined Hidden registers"
45 0x02050038, /* Set coeff idx: 0x38 */
46 0x02048981, /* Set processing coeff: 0x8981 */
47 0x02050045, /* Set coeff idx: 0x45 */
48 0x0204c489, /* Set processing coeff: 0xc489 */
50 0x02050037, /* Set coeff idx: 0x37 */
51 0x02044a05, /* Set processing coeff: 0x4a05 */
52 0x05750003, /* Set coeff idx on NID 0x57?: 0x3 */
53 0x057486a6, /* Set processing coeff on NID 0x57?: 0x86a6 */
55 0x02050046, /* Set coeff idx: 0x46 */
56 0x02040004, /* Set processing coeff: 0x4 */
57 0x0205001b, /* Set coeff idx: 0x1b */
58 0x02040a0b, /* Set processing coeff: 0xa0b */
60 0x02050008, /* Set coeff idx: 0x8 */
61 0x02046a0c, /* Set processing coeff: 0x6a0c */
62 0x02050009, /* Set coeff idx: 0x9 */
63 0x0204e003, /* Set processing coeff: 0xe003 */
65 0x0205000a, /* Set coeff idx: 0xa */
66 0x02047770, /* Set processing coeff: 0x7770 */
67 0x02050040, /* Set coeff idx: 0x40 */
68 0x02049800, /* Set processing coeff: 0x9800 */
70 0x02050010, /* Set coeff idx: 0x10 */
71 0x02040e20, /* Set processing coeff: 0xe20 */
72 0x0205000d, /* Set coeff idx: 0xd */
73 0x02042801, /* Set processing coeff: 0x2801 */
75 0x0143b000, /* Sends unknown verb 0x3B to speaker */
76 0x0143b000, /* Repeated for units? */
77 0x01470740, /* Set widget control on speaker: Output; VrefEn: Hi-Z (disabled) */
78 0x01470740, /* Repeated for units? */
80 0x01470740, /* Repeated for units? */
81 0x01470740, /* Repeated for units? */
82 0x02050010, /* Set coeff idx: 0x10 */
83 0x02040f20, /* Set processing coeff: 0xf20 */
85 /* --- Codec #2 --- */
86 /* coreboot specific header */
87 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */
88 0x80860101, /* Subsystem ID */
89 5, /* Number of jacks (NID entries) */
91 /* Codec Address: Bits 31:28 */
92 /* Node ID: Bits 27:20 */
93 /* Verb ID: Bits 19:8 */
94 /* Payload: Bits 7:0 */
96 /* NOTE: Corrected the table in vendor FW, using codec address 0x2, not 0x0 */
98 /* Enable the third converter and pin first */
99 0x20878101,
100 0x20878101,
101 0x20878101,
102 0x20878101,
104 /* Pin Widget Verb Table */
105 AZALIA_PIN_CFG(2, 0x05, 0x18560010),
106 AZALIA_PIN_CFG(2, 0x06, 0x18560020),
107 AZALIA_PIN_CFG(2, 0x07, 0x18560030),
109 /* Disable the third converter and third pin */
110 0x20878100,
111 0x20878100,
112 0x20878100,
113 0x20878100,
116 const u32 pc_beep_verbs[] = {};
118 AZALIA_ARRAY_SIZES;