src/mainboard/amd/bilby/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <amdblocks/acpi.h>
   6 #include <amdblocks/amd_pci_util.h>
   7 #include <FspsUpd.h>
   8 #include <gpio.h>
   9 #include <soc/cpu.h>
  10 #include <soc/southbridge.h>
  11 #include <soc/pci_devs.h>
  12 #include <soc/platform_descriptors.h>
  13 #include <static.h>
  14 #include <types.h>
  15 #include <commonlib/helpers.h>
  16 #include <soc/amd/picasso/chip.h>
  17 #include "gpio.h"
  18 #include "mainboard.h"
  19
  20 #define MAINBOARD_SHARED_DDI_PORTS 2
  21
  22 /* TODO: recheck IRQ tables */
  23
  24 /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
  25    accessed via I/O ports 0xc00/0xc01. */
  26 static const struct fch_irq_routing fch_irq_map[] = {
  27         { PIRQ_A,       8,              16 },
  28         { PIRQ_B,       10,             17 },
  29         { PIRQ_C,       11,             18 },
  30         { PIRQ_D,       12,             19 },
  31         { PIRQ_SCI,     ACPI_SCI_IRQ,   ACPI_SCI_IRQ },
  32         { PIRQ_SD,      PIRQ_NC,        16 },
  33         { PIRQ_SDIO,    PIRQ_NC,        16 },
  34         { PIRQ_SATA,    PIRQ_NC,        19 },
  35         { PIRQ_EMMC,    PIRQ_NC,        17 },
  36         { PIRQ_GPIO,     7,              7 },
  37         { PIRQ_I2C2,     6,              6 },
  38         { PIRQ_I2C3,    14,             14 },
  39         { PIRQ_UART0,    4,              4 },
  40         { PIRQ_UART1,    3,              3 },
  41         { PIRQ_UART2,    4,              4 },
  42         { PIRQ_UART3,    3,              3 },
  43
  44         /* The MISC registers are not interrupt numbers */
  45         { PIRQ_MISC,    0xfa,           0x00 },
  46         { PIRQ_MISC0,   0x91,           0x00 },
  47         { PIRQ_MISC1,   0x00,           0x00 },
  48         { PIRQ_MISC2,   0x00,           0x00 },
  49 };
  50
  51 const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
  52 {
  53         *length = ARRAY_SIZE(fch_irq_map);
  54         return fch_irq_map;
  55 }
  56
  57 static void program_display_sel_gpios(void)
  58 {
  59         int idx, port_type;
  60         gpio_t display_sel[MAINBOARD_SHARED_DDI_PORTS] = {GPIO_29, GPIO_31};
  61
  62         for (idx = 0; idx < MAINBOARD_SHARED_DDI_PORTS; idx++) {
  63                 port_type = get_ddi_port_conn_type(idx);
  64
  65                 if (port_type == HDMI)
  66                         gpio_output(display_sel[idx], 0);
  67                 else if (port_type == DP)
  68                         gpio_output(display_sel[idx], 1);
  69         }
  70 }
  71
  72 static void mainboard_init(void *chip_info)
  73 {
  74         struct soc_amd_picasso_config *cfg = config_of_soc();
  75
  76         if (!CONFIG(BILBY_LPC))
  77                 cfg->emmc_config.timing = SD_EMMC_EMMC_HS400;
  78
  79         mainboard_program_gpios();
  80
  81         program_display_sel_gpios();
  82
  83         /* Re-muxing LPCCLK0 can hang the system if LPC is in use. */
  84         if (CONFIG(BILBY_LPC))
  85                 printk(BIOS_INFO, "eMMC not available due to LPC requirement\n");
  86         else
  87                 mainboard_program_emmc_gpios();
  88 }
  89
  90 struct chip_operations mainboard_ops = {
  91         .init = mainboard_init,
  92 };