mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / amd / gardenia / devicetree.cb
blob786003f7539c97bb5e4f7603a18636a15eacb4ea
1 # SPDX-License-Identifier: GPL-2.0-only
3 chip soc/amd/stoneyridge
5 register "spd_addr_lookup" = "
7 { {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1
8 }"
10 device domain 0 on
11 subsystemid 0x1022 0x1410 inherit
12 device ref iommu on end
13 device ref gfx on end
14 device ref gfx_hda on end
15 device ref gpp_bridge_0 on end # x4 PCIe slot
16 device ref gpp_bridge_1 on end # M.2 slot
17 device ref gpp_bridge_3 on end # x1 PCIe slot
18 device ref gpp_bridge_4 on end # Cardreader
19 device ref hda_bridge on end
20 device ref hda on end
21 device ref xhci on end
22 device ref sata on end
23 device ref ehci on end
24 device ref sdhci on end
25 end #domain
26 end #chip soc/amd/stoneyridge