mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / amd / onyx_poc / Kconfig
blobf77bfce14bdf7c37b9f84f93158c903f9dcea392
1 ## SPDX-License-Identifier: GPL-2.0-only
3 if BOARD_AMD_ONYX_POC
5 config BOARD_SPECIFIC_OPTIONS
6         def_bool y
7         select SOC_AMD_GENOA_POC
8         select BOARD_ROMSIZE_KB_32768
9         select AMD_SOC_CONSOLE_UART
11 config FMDFILE
12         default "src/mainboard/amd/onyx_poc/board.fmd"
15 config MAINBOARD_DIR
16         default "amd/onyx_poc"
18 config MAINBOARD_PART_NUMBER
19         default "Onyx_poc"
21 # Use BMC SOL console on SoC UART1 by default
22 config UART_FOR_CONSOLE
23         default 1
25 endif