src/mainboard/amd/pademelon/bootblock/OemCustomize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/agesawrapper.h>
   4
   5 /*
   6  * TODO:
   7  * Check if a separate PCIe port list is needed for Prairie Falcon APUs. Only Merlin Falcon has
   8  * PCIe root ports on the functions of bus 0 device 3.
   9  */
  10
  11 static const PCIe_PORT_DESCRIPTOR PortList[] = {
  12         /*
  13          * Init Port descriptor (PCIe port, Lanes 8-15,
  14          * PCI Device Number 3, ...)
  15          */
  16         {
  17                 0,
  18                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15),
  19                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
  20                                 3, 1,
  21                                 HotplugDisabled,
  22                                 PcieGenMaxSupported,
  23                                 PcieGenMaxSupported,
  24                                 AspmDisabled, 0x02, 0)
  25         },
  26
  27         /*
  28          * Initialize Port descriptor (PCIe port, Lane 7,
  29          * PCI Device Number 2, ...)
  30          */
  31         {
  32                 0,
  33                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
  34                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
  35                                 2, 5,
  36                                 HotplugDisabled,
  37                                 PcieGenMaxSupported,
  38                                 PcieGenMaxSupported,
  39                                 AspmDisabled, 0x03, 0)
  40         },
  41         /*
  42          * Initialize Port descriptor (PCIe port, Lane 6,
  43          * PCI Device Number 2, ...)
  44          */
  45         {
  46                 0,
  47                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
  48                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
  49                                 2, 4,
  50                                 HotplugDisabled,
  51                                 PcieGenMaxSupported,
  52                                 PcieGenMaxSupported,
  53                                 AspmDisabled, 0x04, 0)
  54         },
  55         /*
  56          * Initialize Port descriptor (PCIe port, Lane 5,
  57          * PCI Device Number 2, ...)
  58          */
  59         {
  60                 0,
  61                 PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 5, 5),
  62                 PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
  63                                 2, 3,
  64                                 HotplugDisabled,
  65                                 PcieGenMaxSupported,
  66                                 PcieGenMaxSupported,
  67                                 AspmDisabled, 0x04, 0)
  68         },
  69         /*
  70          * Initialize Port descriptor (PCIe port, Lane4,
  71          * PCI Device Number 2, ...)
  72          */
  73         {
  74                 0,
  75                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
  76                 PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
  77                                 2, 2,
  78                                 HotplugDisabled,
  79                                 PcieGenMaxSupported,
  80                                 PcieGenMaxSupported,
  81                                 AspmDisabled, 0x06, 0)
  82         },
  83         /*
  84          * Initialize Port descriptor (PCIe port, Lanes 0-3,
  85          * PCI Device Number 2, ...)
  86          */
  87         {
  88                 /*
  89                  * Descriptor flags  !!!IMPORTANT!!! Terminate last element
  90                  * of array
  91                  */
  92                 DESCRIPTOR_TERMINATE_LIST,
  93                 PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 3),
  94                 PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
  95                                 2, 1,
  96                                 HotplugDisabled,
  97                                 PcieGenMaxSupported,
  98                                 PcieGenMaxSupported,
  99                                 AspmDisabled, 0x07, 0)
 100         },
 101
 102 };
 103
 104 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
 105         /* DP0 */
 106         {
 107                 0,
 108                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
 109                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
 110         },
 111         /* DP1 */
 112         {
 113                 0,
 114                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 20, 23),
 115                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
 116         },
 117         /* DP2 */
 118         {
 119                 DESCRIPTOR_TERMINATE_LIST,
 120                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
 121                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
 122         },
 123 };
 124
 125 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 126         .Flags        = DESCRIPTOR_TERMINATE_LIST,
 127         .SocketId     = 0,
 128         .PciePortList = (void *)PortList,
 129         .DdiLinkList  = (void *)DdiList
 130 };
 131
 132 /*---------------------------------------------------------------------------*/
 133 /**
 134  *  OemCustomizeInitEarly
 135  *
 136  *  Description:
 137  *    This is the stub function will call the host environment through the
 138  *    binary block interface (call-out port) to provide a user hook opportunity.
 139  *
 140  *  Parameters:
 141  *    @param[in]      **PeiServices
 142  *    @param[in]      *InitEarly
 143  *
 144  *    @retval         VOID
 145  *
 146  **/
 147 /*---------------------------------------------------------------------------*/
 148 VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly)
 149 {
 150         InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
 151 }