mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / amd / pademelon / hda_verb.c
blob5bef966e75a488f82d5567928a89a0a4760a0d54
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <device/azalia_device.h>
5 const u32 cim_verb_data[] = {
6 /* coreboot specific header */
7 /* Realtek ALC662 rev1 */
8 0x10ec0662, /* Vendor ID */
9 0x80865756, /* Subsystem ID */
10 10, /* Number of entries */
12 /* Pin Widget Verb Table */
14 AZALIA_PIN_CFG(0, 0x14, 0x01014010),
15 AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
16 AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
17 AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
18 AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
19 AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
20 AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
21 AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
22 AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
23 AZALIA_PIN_CFG(0, 0x1e, 0x01441130),
26 const u32 pc_beep_verbs[0] = {};
28 AZALIA_ARRAY_SIZES;