src/mainboard/aoostar/wtr_r1/devicetree.cb

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/intel/alderlake
   4
   5         # GPE configuration
   6         # Note that GPE events called out in ASL code rely on this
   7         # route. i.e. If this route changes then the affected GPE
   8         # offset bits also need to be changed.
   9         register "pmc_gpe0_dw0" = "GPP_B"
  10         register "pmc_gpe0_dw1" = "GPP_D"
  11         register "pmc_gpe0_dw2" = "GPP_E"
  12
  13         register "sagv" = "SaGv_Enabled"
  14
  15         register "dptf_enable" = "1"
  16
  17         register "s0ix_enable" = "true"
  18
  19         register "common_soc_config" = "{
  20                 .i2c[0] = {
  21                         .speed = I2C_SPEED_FAST,
  22                 },
  23                 .i2c[1] = {
  24                         .speed = I2C_SPEED_FAST,
  25                 },
  26                 .i2c[2] = {
  27                         .speed = I2C_SPEED_FAST,
  28                 },
  29                 .i2c[3] = {
  30                         .speed = I2C_SPEED_FAST,
  31                 },
  32                 .i2c[5] = {
  33                         .speed = I2C_SPEED_FAST,
  34                 },
  35         }"
  36
  37         # Configure external V1P05/Vnn/VnnSx Rails
  38         register "ext_fivr_settings" = "{
  39                 .configure_ext_fivr = 1,
  40                 .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
  41                 .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
  42                 .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
  43                 .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
  44                 .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
  45                 .v1p05_voltage_mv = 1050,
  46                 .vnn_voltage_mv = 780,
  47                 .vnn_sx_voltage_mv = 1050,
  48                 .v1p05_icc_max_ma = 500,
  49                 .vnn_icc_max_ma = 500,
  50         }"
  51
  52         device domain 0 on
  53                 device ref igpu on
  54                         register "ddi_portA_config" = "1"
  55                         register "ddi_portB_config" = "1"
  56                         register "ddi_ports_config" = "{
  57                                 [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  58                                 [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
  59                         }"
  60                 end
  61                 device ref dtt on end
  62                 device ref crashlog off end
  63                 device ref tcss_xhci on
  64                         register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)"     # USB3/2 Type A upper
  65                 end
  66                 device ref xhci on
  67                         register "usb2_ports" = "{
  68                                 [0] = USB2_PORT_TYPE_C(OC0),            /* Type-C */
  69                                 [1] = USB2_PORT_MID(OC_SKIP),           /* microSD card reader */
  70                                 [2] = USB2_PORT_MID(OC3),               /* USB2 Type A upper */
  71                                 [3] = USB2_PORT_MID(OC3),               /* USB2 Type A lower */
  72                                 [4] = USB2_PORT_MID(OC3),               /* USB3/2 Type A upper */
  73                                 [5] = USB2_PORT_MID(OC3),               /* USB3/2 Type A lower */
  74                                 [7] = USB2_PORT_MID(OC_SKIP),           /* M.2 WLAN */
  75                         }"
  76
  77                         register "usb3_ports" = "{
  78                                 [0] = USB3_PORT_DEFAULT(OC0),           /* Type-C */
  79                                 [1] = USB3_PORT_DEFAULT(OC_SKIP),       /* microSD card reader */
  80                                 [5] = USB3_PORT_DEFAULT(OC3),           /* USB3/2 Type A lower */
  81                                 [6] = USB3_PORT_DEFAULT(OC3),           /* USB3/2 Type A upper */
  82                         }"
  83                 end
  84                 device ref cnvi_wifi on
  85                         register "cnvi_bt_core" = "true"
  86                         register "cnvi_bt_audio_offload" = "true"
  87                         chip drivers/wifi/generic
  88                                 register "wake" = "GPE0_PME_B0"
  89                                 device generic 0 on end
  90                         end
  91                 end
  92                 device ref i2c0 on
  93                         register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
  94                 end
  95                 device ref i2c1 on
  96                         register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
  97                 end
  98                 device ref i2c2 on
  99                         register "serial_io_i2c_mode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
 100                 end
 101                 device ref i2c3 on
 102                         register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
 103                 end
 104                 device ref sata on
 105                         register "sata_salp_support" = "1"
 106                         register "sata_ports_enable" = "{
 107                                 [0] = 1,
 108                                 [1] = 1,
 109                         }"
 110                         register "sata_ports_dev_slp" = "{
 111                                 [0] = 1,
 112                                 [1] = 1,
 113                         }"
 114                 end
 115                 device ref i2c5 on
 116                         register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci"
 117                 end
 118                 device ref pcie_rp3 on
 119                         register "pch_pcie_rp[PCH_RP(3)]" = "{
 120                                 .clk_src = 2,
 121                                 .clk_req = 2,
 122                                 .flags = PCIE_RP_CLK_REQ_DETECT,
 123                         }"
 124                         smbios_slot_desc        "SlotTypeM2Socket3" "SlotLengthOther"
 125                                                 "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X"
 126                 end
 127                 device ref pcie_rp7 on  # LAN1
 128                         register "pch_pcie_rp[PCH_RP(7)]" = "{
 129                                 .clk_src = 3,
 130                                 .clk_req = 3,
 131                                 .flags = PCIE_RP_CLK_REQ_DETECT,
 132                         }"
 133                 end
 134                 device ref pcie_rp9 on  # LAN2
 135                         register "pch_pcie_rp[PCH_RP(9)]" = "{
 136                                 .clk_src = 0,
 137                                 .clk_req = 0,
 138                                 .flags = PCIE_RP_CLK_REQ_DETECT,
 139                         }"
 140                 end
 141                 device ref pcie_rp10 on
 142                         register "pch_pcie_rp[PCH_RP(10)]" = "{
 143                                 .clk_src = 1,
 144                                 .clk_req = 1,
 145                                 .flags = PCIE_RP_CLK_REQ_DETECT,
 146                         }"
 147                         smbios_slot_desc        "SlotTypeM2Socket1_SD" "SlotLengthOther"
 148                                                 "M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X"
 149                 end
 150                 device ref pch_espi on
 151                         # Needed for ITE SuperIO
 152                         register "gen1_dec" = "0x00fc0201"
 153                         register "gen2_dec" = "0x007c0a01"
 154                         register "gen3_dec" = "0x000c03e1"
 155                         register "gen4_dec" = "0x001c02e1"
 156                         chip superio/ite/it8613e
 157                                 register "TMPIN1.mode"   = "THERMAL_RESISTOR"
 158                                 register "ec.vin_mask"   = "VIN_ALL"
 159                                 # CPU_FAN1
 160                                 register "FAN2.mode" = "FAN_SMART_AUTOMATIC"
 161                                 register "FAN2.smart.tmpin"     = " 1"
 162                                 register "FAN2.smart.tmp_off"   = "32" # Vendor default: 30
 163                                 register "FAN2.smart.tmp_start" = "35"
 164                                 register "FAN2.smart.tmp_full"  = "96"
 165                                 register "FAN2.smart.tmp_delta" = " 1" # Vendor default: 2
 166                                 register "FAN2.smart.pwm_start" = "30" # Vendor default: 40
 167                                 register "FAN2.smart.slope"     = " 1"
 168                                 # SYSFANCN1
 169                                 register "FAN3.mode" = "FAN_SMART_SOFTWARE"
 170                                 register "FAN3.smart.pwm_start" = "80"
 171                                 # SYS_FAN1
 172                                 register "FAN4.mode" = "FAN_SMART_SOFTWARE"
 173                                 register "FAN4.smart.pwm_start" = "127"
 174
 175                                 device pnp 2e.0 off end # Floppy
 176                                 device pnp 2e.1 off end # COM 1
 177                                 device pnp 2e.4 on      # Environment Controller
 178                                         io 0x60 = 0xa30
 179                                         io 0x62 = 0xa20
 180                                         irq 0x70 = 0x00
 181                                 end
 182                                 device pnp 2e.5 off end # Keyboard
 183                                 device pnp 2e.6 off end # Mouse
 184                                 device pnp 2e.7 on      # GPIO
 185                                         io 0x60 = 0x000
 186                                         io 0x62 = 0xa00
 187                                         irq 0x70 = 0x00
 188                                         irq 0x71 = 0x01
 189                                 end
 190                                 device pnp 2e.a off end # CIR
 191                         end
 192                 end
 193                 device ref uart0 on
 194                         register "serial_io_uart_mode" = "{
 195                                 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 196                         }"
 197                 end
 198                 device ref gspi0 on
 199                         register "serial_io_gspi_mode" = "{
 200                                 [PchSerialIoIndexGSPI0] = PchSerialIoPci,
 201                         }"
 202                 end
 203                 device ref ish on end
 204                 device ref hda on
 205                         register "pch_hda_dsp_enable" = "1"
 206                         register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
 207                         register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 208                         register "pch_hda_idisp_codec_enable" = "1"
 209                 end
 210                 device ref smbus on end
 211         end
 212 end