mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3

[coreboot2.git] / src / mainboard / apple / macbookair4_2 / devicetree.cb

chip northbridge/intel/sandybridge
        device domain 0 on
                chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
                        register "gen1_dec" = "0x000c0681"
                        register "gen2_dec" = "0x000c1641"
                        register "gen3_dec" = "0x001c0301"
                        register "gen4_dec" = "0x00fc0701"
                        register "gpi7_routing" = "2"
                        register "pcie_port_coalesce" = "true"
                        register "sata_interface_speed_support" = "0x3"
                        register "sata_port_map" = "0x1"
                        register "usb_port_config" = "{
                                {1, 0, -1}, /* USB HUB 1 */
                                {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, /* Unused x7 */
                                {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, {0, 0, -1},
                                {1, 0, -1}, /* USB HUB 2 */
                                {1, 0, -1}, /* Camera */
                                {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, {0, 0, -1} /* Unused x4 */
                        }"
                        device ref mei1 on
                                subsystemid 0x8086 0x7270
                        end
                        device ref ehci2 on
                                subsystemid 0x8086 0x7270
                        end
                        device ref hda on
                                subsystemid 0x8086 0x7270
                        end
                        device ref pcie_rp1 on
                                subsystemid 0x8086 0x7270
                        end
                        device ref pcie_rp2 on
                                subsystemid 0x8086 0x7270
                        end
                        device ref ehci1 on
                                subsystemid 0x8086 0x7270
                        end
                        device ref lpc on
                                subsystemid 0x8086 0x7270
                        end
                        device ref sata1 on
                                subsystemid 0x8086 0x7270
                        end
                        device ref smbus on
                                subsystemid 0x8086 0x7270
                        end
                end
                device ref host_bridge on
                        subsystemid 0x106b 0x00eb
                end
                device ref peg10 on
                        subsystemid 0x106b 0x00eb
                end
                device ref igd on
                        subsystemid 0x106b 0x00eb
                        register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }"
                        register "gfx.ndid" = "2"
                        register "gfx.use_spread_spectrum_clock" = "1"
                        register "gpu_cpu_backlight" = "0x00001312"
                        register "gpu_dp_b_hotplug" = "4"
                        register "gpu_dp_c_hotplug" = "4"
                        register "gpu_dp_d_hotplug" = "4"
                        register "gpu_panel_port_select" = "PANEL_PORT_DP_A"
                        register "gpu_panel_power_backlight_off_delay" = "2000"
                        register "gpu_panel_power_backlight_on_delay" = "10"
                        register "gpu_panel_power_cycle_delay" = "6"
                        register "gpu_panel_power_down_delay" = "500"
                        register "gpu_panel_power_up_delay" = "2000"
                        register "gpu_pch_backlight" = "0x13121312"
                end
                device pci 1a.7 on
                        subsystemid 0x8086 0x7270
                end
                device pci 1d.7 on
                        subsystemid 0x8086 0x7270
                end
        end
end