mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / apple / macbookair4_2 / hda_verb.c
blobd2acefbaa77e3b078b847b1babbb9d75aae41572
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/azalia_device.h>
5 const u32 cim_verb_data[] = {
6 0x10134206, /* Codec Vendor / Device ID: Cirrus */
7 0x106b5b00, /* Subsystem ID */
8 11, /* Number of 4 dword sets */
9 AZALIA_SUBVENDOR(0, 0x106b5b00),
10 AZALIA_PIN_CFG(0, 0x09, 0x012b4030),
11 AZALIA_PIN_CFG(0, 0x0a, 0x400000f0),
12 AZALIA_PIN_CFG(0, 0x0b, 0x90100120),
13 AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
14 AZALIA_PIN_CFG(0, 0x0d, 0x90a00110),
15 AZALIA_PIN_CFG(0, 0x0e, 0x400000f0),
16 AZALIA_PIN_CFG(0, 0x0f, 0x400000f0),
17 AZALIA_PIN_CFG(0, 0x10, 0x400000f0),
18 AZALIA_PIN_CFG(0, 0x12, 0x400000f0),
19 AZALIA_PIN_CFG(0, 0x15, 0x400000f0),
21 0x80862805, /* Codec Vendor / Device ID: Intel */
22 0x80860101, /* Subsystem ID */
23 4, /* Number of 4 dword sets */
24 AZALIA_SUBVENDOR(3, 0x80860101),
25 AZALIA_PIN_CFG(3, 0x05, 0x18560010),
26 AZALIA_PIN_CFG(3, 0x06, 0x18560010),
27 AZALIA_PIN_CFG(3, 0x07, 0x18560010),
30 const u32 pc_beep_verbs[0] = {};
32 AZALIA_ARRAY_SIZES;