src/mainboard/arm/rdn2/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include "chip.h"
   4 #include <acpi/acpigen.h>
   5 #include <arch/mmu.h>
   6 #include <bootmem.h>
   7 #include <cbfs.h>
   8 #include <device/device.h>
   9 #include <mainboard/addressmap.h>
  10 #include <ramdetect.h>
  11 #include <stdint.h>
  12 #include <symbols.h>
  13
  14 static size_t ram_size(void)
  15 {
  16         return (size_t)cbmem_top() - (uintptr_t)_dram;
  17 }
  18
  19 static size_t ram2_size(void)
  20 {
  21         return (size_t)probe_ramsize((uintptr_t)RDN2_DRAM2_BASE, RDN2_DRAM2_SIZE) * MiB;
  22 }
  23
  24 static void mainboard_init(void *chip_info)
  25 {
  26         mmu_config_range(_dram, ram_size(), MA_MEM | MA_RW);
  27         mmu_config_range((void *)RDN2_DRAM2_BASE, ram2_size(), MA_MEM | MA_RW);
  28 }
  29
  30 DECLARE_REGION(fdt_pointer)
  31
  32 void smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count)
  33 {
  34         *core_count = 0;
  35         struct device *dev = NULL;
  36         while ((dev = dev_find_path(dev, DEVICE_PATH_GICC_V3)))
  37                 *core_count += 1;
  38
  39         *thread_count = 1;
  40 }
  41
  42
  43 static void rdn2_aarch64_init(struct device *dev)
  44 {
  45         struct memory_info *mem_info;
  46
  47         mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
  48         if (mem_info == NULL)
  49                 return;
  50
  51         memset(mem_info, 0, sizeof(*mem_info));
  52
  53         mem_info->ecc_type = MEMORY_ARRAY_ECC_UNKNOWN;
  54         mem_info->max_capacity_mib = 0x800000;
  55         mem_info->number_of_devices = mem_info->dimm_cnt = 1;
  56
  57         mem_info->dimm[0].dimm_size = (ram_size() + ram2_size()) / MiB;
  58         mem_info->dimm[0].ddr_type = MEMORY_TYPE_DRAM;
  59         mem_info->dimm[0].ddr_frequency = 0;
  60         mem_info->dimm[0].channel_num = mem_info->dimm[0].dimm_num = 0;
  61         mem_info->dimm[0].bank_locator = 0;
  62
  63         mem_info->dimm[0].bus_width = 0x03;     // 64-bit, no parity
  64         mem_info->dimm[0].vdd_voltage = 0;
  65         mem_info->dimm[0].max_speed_mts = mem_info->dimm[0].configured_speed_mts = 0;
  66 }
  67
  68 static unsigned long mb_write_acpi_tables(const struct device *dev, unsigned long current,
  69                                           acpi_rsdp_t *rsdp)
  70 {
  71         printk(BIOS_DEBUG, "ACPI:    * DBG2\n");
  72         return acpi_pl011_write_dbg2_uart(rsdp, current, RDN2_UART_NS_BASE, "\\_SB.COM0");
  73 }
  74
  75
  76 static void mainboard_enable(struct device *dev)
  77 {
  78         dev->ops->init = rdn2_aarch64_init;
  79         dev->ops->write_acpi_tables = mb_write_acpi_tables;
  80 }
  81
  82
  83 struct chip_operations mainboard_ops = {
  84         .init = mainboard_init,
  85         .enable_dev = mainboard_enable,
  86 };
  87
  88 struct chip_operations mainboard_arm_rdn2_ops = { };
  89
  90 static void rdn2_aarch64_domain_read_resources(struct device *dev)
  91 {
  92         struct resource *res;
  93         int index = 0;
  94
  95         /* Initialize the system-wide I/O space constraints. */
  96         res = new_resource(dev, index++);
  97         res->limit = 0xffffUL;
  98         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
  99
 100         /* Initialize the system-wide memory resources constraints. */
 101         res = new_resource(dev, index++);
 102         res->base = RDN2_PCIE_MMIO_BASE;
 103         res->limit = RDN2_PCIE_MMIO_LIMIT;
 104         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
 105
 106         res = new_resource(dev, index++);
 107         res->base = RDN2_PCIE_MMIO_HIGH_BASE;
 108         res->limit = RDN2_PCIE_MMIO_HIGH_LIMIT;
 109         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
 110
 111         ram_range(dev, index++, (uintptr_t)_dram, ram_size());
 112         reserved_ram_range(dev, index++, (uintptr_t)RDN2_SECMEM_BASE, RDN2_SECMEM_SIZE);
 113
 114         ram_range(dev, index++, (uintptr_t)RDN2_DRAM2_BASE, ram2_size());
 115
 116         mmio_range(dev, index++, RDN2_FLASH_BASE, RDN2_FLASH_SIZE);
 117 }
 118
 119 struct device_operations rdn2_aarch64_pci_domain_ops = {
 120         .read_resources    = rdn2_aarch64_domain_read_resources,
 121         .set_resources     = pci_domain_set_resources,
 122         .scan_bus          = pci_host_bridge_scan_bus,
 123 };
 124
 125 static void rdn2_fill_cpu_ssdt(const struct device *dev)
 126 {
 127         acpigen_write_processor_device(dev->path.gicc_v3.mpidr);
 128         acpigen_write_processor_device_end();
 129 }
 130
 131 struct device_operations rdn2_cpu_ops = {
 132         .acpi_fill_ssdt = rdn2_fill_cpu_ssdt,
 133 };
 134
 135 static void rdn2_aarch64_scan_bus(struct device *dev)
 136 {
 137         u16 i = 0;
 138         struct bus *bus = alloc_bus(dev);
 139
 140         for (i = 0; i < 16; i++) {
 141                 printk(BIOS_DEBUG, "Allocating CPU %d\n", i);
 142                 struct device_path devpath = { .type = DEVICE_PATH_GICC_V3,
 143                         .gicc_v3 = { .mpidr = i << 16,
 144                                      .vgic_mi = 0x19,
 145                                      .pi_gsiv = 0x17, },
 146                 };
 147                 struct device *cpu = alloc_dev(bus, &devpath);
 148                 assert(cpu);
 149                 cpu->ops = &rdn2_cpu_ops;
 150         }
 151
 152 }
 153
 154 struct device_operations rdn2_aarch64_cpu_ops = {
 155         .scan_bus = rdn2_aarch64_scan_bus,
 156 };