src/mainboard/arm/rdn2/pptt.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <stdlib.h>
   4 #include <cpu/cpu.h>
   5 #include <arch/cache.h>
   6 #include <acpi/acpi.h>
   7 #include <console/console.h>
   8
   9 #define CACHE_NODE_FLAGS 0xd7 // everything valid except, write-policy and allocation type
  10 #define CLUSTER_FLAGS    0x11 // physical package, ID invalid, no thread, no leaf, identical impl.
  11 #define CORE_FLAGS       0x0a // no physical package, ID valid, no thread, leaf.
  12 #define CORE_FLAGS_1       0x12 // no physical package, ID valid, no thread, identical i.
  13
  14 /*
  15  * L2 cache (LLC)
  16  */
  17 struct pptt_cache l2 = {
  18
  19         .next_level = NULL
  20 };
  21
  22 /*
  23  * L1D cache
  24  */
  25 struct pptt_cache l1d = {
  26         .next_level = &l2
  27 };
  28
  29 /*
  30  * L1I cache
  31  */
  32 struct pptt_cache l1i = {
  33         //.sibling = &l1d,
  34         .next_level = &l2
  35 };
  36
  37 /*
  38  * private resources of a cpu core. Same for
  39  * each core, thus we can reuse this struture
  40  * instead of creating it dynamically.
  41  */
  42 struct pptt_cpu_resources core_resources = {
  43         .cache = &l1i,
  44 };
  45
  46 struct pptt_topology root_topology = {
  47
  48         .flags.raw = CLUSTER_FLAGS,
  49         .resources = NULL,
  50         .sibling   = NULL,
  51
  52         .child     = &(struct pptt_topology) {
  53
  54                 .processor_id = 0,
  55                 .flags.raw    = CORE_FLAGS_1,
  56
  57                 .resources = NULL,
  58
  59                 .child     = &(struct pptt_topology) {
  60                         .processor_id = 0,
  61                         .flags.raw    = CORE_FLAGS,
  62
  63                         .resources = &(struct pptt_cpu_resources) {
  64
  65                                 .cache = &l1i,
  66
  67                         },
  68
  69                         .sibling   = NULL,
  70                         .child   = NULL,
  71                 },
  72                 .sibling   = NULL, // updated in runtime
  73         }
  74 };
  75
  76 /* --- Helpers --- */
  77
  78 static u8 cache_attributes(const enum cache_type type)
  79 {
  80         /*
  81          * 'write-policy' and 'allocation type' currently
  82          * unsupported. cache flags set accordingly.
  83          *
  84          * maybe a todo for the future.
  85          */
  86
  87         u8 attr = 0x0;
  88
  89         if (type == CACHE_INSTRUCTION)
  90                 attr |= (0x1 << 2);
  91         else if (type == CACHE_UNIFIED)
  92                 attr |= (0x1 << 3);
  93
  94         return attr;
  95 }
  96
  97 /* --- ACPI hook --- */
  98
  99 struct pptt_topology *acpi_get_pptt_topology(void)
 100 {
 101         struct cache_info info;
 102
 103         /* Dump Cache info */
 104         for (int cache_level = CACHE_L1; cache_level <= CACHE_L7; cache_level++) {
 105                 int cache_type = cpu_get_cache_type(cache_level);
 106                 if (cache_type == NO_CACHE)
 107                         continue;
 108
 109                 if (cache_type == CACHE_SEPARATE) {
 110                         printk(BIOS_DEBUG, "Fetching cache info for: level:%d, type:%d\n",
 111                                cache_level, cache_type);
 112                         cpu_get_cache_info(cache_level, cache_type, &info);
 113                         printk(BIOS_DEBUG, "Size: %lld, associativity: %lld\n", info.size,
 114                                info.associativity);
 115
 116                         cache_type = CACHE_INSTRUCTION;
 117
 118                         printk(BIOS_DEBUG, "Fetching cache info for: level:%d, type:%d\n",
 119                                cache_level, cache_type);
 120                         cpu_get_cache_info(cache_level, cache_type, &info);
 121                         printk(BIOS_DEBUG, "Size: %lld, associativity: %lld\n", info.size,
 122                                info.associativity);
 123
 124                         cache_type = CACHE_DATA;
 125                 }
 126
 127                 printk(BIOS_DEBUG, "Fetching cache info for: level:%d, type:%d\n", cache_level,
 128                        cache_type);
 129                 cpu_get_cache_info(cache_level, cache_type, &info);
 130                 printk(BIOS_DEBUG, "Size: %lld, associativity: %lld\n", info.size,
 131                        info.associativity);
 132         }
 133
 134         /* update cache information (L1I) */
 135
 136         cpu_get_cache_info(CACHE_L1, CACHE_INSTRUCTION, &info);
 137
 138         l1i.size          = info.size;
 139         l1i.associativity = info.associativity;
 140         l1i.numsets       = info.numsets;
 141         l1i.line_size     = info.line_bytes;
 142         l1i.attributes    = cache_attributes(CACHE_INSTRUCTION);
 143         l1i.flags.raw     = CACHE_NODE_FLAGS | 0xff;
 144
 145         /* update cache information (L1D) */
 146
 147         cpu_get_cache_info(CACHE_L1, CACHE_DATA, &info);
 148
 149         l1d.size          = info.size;
 150         l1d.associativity = info.associativity;
 151         l1d.numsets       = info.numsets;
 152         l1d.line_size     = info.line_bytes;
 153         l1d.attributes    = cache_attributes(CACHE_DATA) | (0x2);
 154         l1d.flags.raw     = CACHE_NODE_FLAGS | 0xff;
 155
 156         /* update cache information (L2) */
 157
 158         cpu_get_cache_info(CACHE_L2, CACHE_UNIFIED, &info);
 159
 160         l2.size    = info.size;
 161         l2.associativity  = info.associativity;
 162         l2.numsets      = info.numsets;
 163         l2.line_size      = info.line_bytes;
 164         l2.attributes     = cache_attributes(CACHE_UNIFIED) | (0x2);
 165         l2.flags.raw      = CACHE_NODE_FLAGS | 0xff;
 166
 167         /* add secondary CPUs */
 168
 169         u32 cpu_id = 0;
 170
 171         struct device *dev   = NULL;
 172         struct pptt_topology **it = &root_topology.child->sibling;
 173         struct pptt_topology **sibling;
 174
 175         while ((dev = dev_find_path(dev, DEVICE_PATH_GICC_V3))) {
 176                 if (cpu_id == 0) {
 177
 178                         cpu_id += 1;
 179                         continue;
 180                 }
 181
 182                 if ((*it = malloc(sizeof(struct pptt_topology))) == NULL) {
 183
 184                         printk(BIOS_ERR, "Could not allocate pptt structure!\n");
 185                         break;
 186                 }
 187
 188                 memset(*it, 0, sizeof(struct pptt_topology));
 189
 190                 (*it)->processor_id = cpu_id;
 191                 (*it)->flags.raw    = CORE_FLAGS_1;
 192                 (*it)->resources    = NULL;
 193
 194                 //sibling = (*it)->sibling;
 195                 sibling = &(*it)->sibling;
 196
 197                 it = &(*it)->child;
 198
 199                 if ((*it = malloc(sizeof(struct pptt_topology))) == NULL) {
 200
 201                         printk(BIOS_ERR, "Could not allocate pptt structure!\n");
 202                         break;
 203                 }
 204
 205                 memset(*it, 0, sizeof(struct pptt_topology));
 206
 207                 (*it)->processor_id = cpu_id;
 208                 (*it)->flags.raw    = CORE_FLAGS;
 209                 (*it)->resources    = &core_resources;
 210
 211                 //it = &(*it)->sibling;
 212                 it = sibling;
 213
 214                 cpu_id += 1;
 215         }
 216
 217         return &root_topology;
 218 }