mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / asrock / z97e-itx_ac / bootblock.c
blobd16fb395a0f916112dab8e01c29ff020aa61fd8c
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/pnp_ops.h>
4 #include <superio/nuvoton/common/nuvoton.h>
5 #include <superio/nuvoton/nct6776/nct6776.h>
6 #include <southbridge/intel/lynxpoint/pch.h>
7 #define GLOBAL_DEV PNP_DEV(0x2e, 0)
8 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
10 void mainboard_config_superio(void)
12 nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
13 /* Select SIO pin mux states */
14 pnp_write_config(GLOBAL_DEV, 0x1b, 0x48);
15 pnp_write_config(GLOBAL_DEV, 0x24, 0x5c);
16 pnp_write_config(GLOBAL_DEV, 0x27, 0xd0);
17 pnp_write_config(GLOBAL_DEV, 0x2a, 0xe0);
18 pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);
19 pnp_write_config(GLOBAL_DEV, 0x2f, 0x01);
20 nuvoton_pnp_exit_conf_state(GLOBAL_DEV);