| blob | 965fd6f0527f390b134fa31fcf9c597beb8a085a |
1 /* SPDX-License-Identifier: GPL-2.0-only OR X11 */
2 /* Cavium Thunder DTS file - Thunder SoC description */
4 / {
5 model = "Cavium ThunderX CN81XX board";
6 compatible = "cavium,thunder-81xx";
7 interrupt-parent = <&gic0>;
8 #address-cells = <2>;
9 #size-cells = <2>;
11 psci {
12 compatible = "arm,psci-0.2";
13 method = "smc";
14 };
16 cpus {
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
21 cluster0 {
22 core0 {
23 cpu = <&CPU0>;
24 };
25 core1 {
26 cpu = <&CPU1>;
27 };
28 core2 {
29 cpu = <&CPU2>;
30 };
31 core3 {
32 cpu = <&CPU3>;
33 };
34 };
35 };
37 CPU0: cpu@0 {
38 device_type = "cpu";
39 compatible = "cavium,thunder", "arm,armv8";
40 reg = <0x0 0x000>;
41 enable-method = "psci";
42 /* socket 0 */
43 numa-node-id = <0>;
44 next-level-cache = <&thunderx_L2_0>;
45 };
46 CPU1: cpu@1 {
47 device_type = "cpu";
48 compatible = "cavium,thunder", "arm,armv8";
49 reg = <0x0 0x001>;
50 enable-method = "psci";
51 numa-node-id = <0>;
52 next-level-cache = <&thunderx_L2_0>;
53 };
54 CPU2: cpu@2 {
55 device_type = "cpu";
56 compatible = "cavium,thunder", "arm,armv8";
57 reg = <0x0 0x002>;
58 enable-method = "psci";
59 numa-node-id = <0>;
60 next-level-cache = <&thunderx_L2_0>;
61 };
62 CPU3: cpu@3 {
63 device_type = "cpu";
64 compatible = "cavium,thunder", "arm,armv8";
65 reg = <0x0 0x003>;
66 enable-method = "psci";
67 numa-node-id = <0>;
68 next-level-cache = <&thunderx_L2_0>;
69 };
70 };
72 thunderx_L2_0: l2-cache0 {
73 compatible = "cache";
74 numa-node-id = <0>;
75 };
77 timer {
78 compatible = "arm,armv8-timer";
79 interrupts = <1 13 4>,
80 <1 14 4>,
81 <1 11 4>,
82 <1 10 4>;
83 };
85 pmu {
86 compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3";
87 interrupts = <1 7 4>;
88 };
90 mmc_supply_3v3: mmc_supply_3v3 {
91 compatible = "regulator-fixed";
92 regulator-name = "mmc_supply_3v3";
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
96 gpio = <&gpio_6_0 8 0>;
97 enable-active-high;
98 };
100 gic0: interrupt-controller@801000000000 {
101 compatible = "arm,gic-v3";
102 #interrupt-cells = <3>;
103 #address-cells = <2>;
104 #size-cells = <2>;
105 #redistributor-regions = <1>;
106 ranges;
107 interrupt-controller;
108 reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
109 <0x8010 0x80000000 0x0 0x600000>; /* GICR */
110 interrupts = <1 9 4>;
112 its: gic-its@801000020000 {
113 compatible = "arm,gic-v3-its";
114 reg = <0x8010 0x20000 0x0 0x200000>;
115 msi-controller;
116 numa-node-id = <0>;
117 };
118 };
120 soc@0 {
121 compatible = "simple-bus";
122 #address-cells = <2>;
123 #size-cells = <2>;
124 ranges;
125 numa-node-id = <0>;
127 refclkuaa: refclkuaa {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <116640000>;
131 clock-output-names = "refclkuaa";
132 };
134 sclk: sclk {
135 compatible = "fixed-clock";
136 #clock-cells = <0>;
137 clock-frequency = <800000000>;
138 clock-output-names = "sclk";
139 };
141 uaa0: serial@87e028000000 {
142 compatible = "arm,pl011", "arm,primecell";
143 reg = <0x87e0 0x28000000 0x0 0x1000>;
144 interrupts = <0 5 4>;
145 clocks = <&refclkuaa>;
146 clock-names = "apb_pclk";
147 skip-init;
148 };
150 uaa1: serial@87e029000000 {
151 compatible = "arm,pl011", "arm,primecell";
152 reg = <0x87e0 0x29000000 0x0 0x1000>;
153 interrupts = <0 6 4>;
154 clocks = <&refclkuaa>;
155 clock-names = "apb_pclk";
156 skip-init;
157 };
159 uaa2: serial@87e02a000000 {
160 compatible = "arm,pl011", "arm,primecell";
161 reg = <0x87e0 0x2a000000 0x0 0x1000>;
162 interrupts = <0 7 4>;
163 clocks = <&refclkuaa>;
164 clock-names = "apb_pclk";
165 skip-init;
166 };
168 uaa3: serial@87e02b000000 {
169 compatible = "arm,pl011", "arm,primecell";
170 reg = <0x87e0 0x2b000000 0x0 0x1000>;
171 interrupts = <0 8 4>;
172 clocks = <&refclkuaa>;
173 clock-names = "apb_pclk";
174 skip-init;
175 };
177 watch-dog@8440000a0000 {
178 compatible = "arm,sbsa-gwdt";
179 reg = <0x8440 0xa0000 0x0 0x1000>, <0x8440 0xb0000 0x0 0x1000>;
180 interrupts = <0 9 4>;
181 };
183 pbus0: nor@0 {
184 compatible = "cfi-flash";
185 reg = <0x8000 0x0 0x0 0x800000>;
186 device-width = <1>;
187 bank-width = <1>;
188 clocks = <&sclk>;
189 };
191 smmu0@830000000000 {
192 compatible = "cavium,smmu-v2";
193 reg = <0x8300 0x0 0x0 0x2000000>;
194 #global-interrupts = <1>;
195 interrupts = <0 68 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
196 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
197 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
198 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
199 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
200 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
201 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
202 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
203 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
204 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>,
205 <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>;
207 mmu-masters = <&ecam0 0x100>,
208 <&pem0 0x200>,
209 <&pem1 0x300>,
210 <&pem2 0x400>;
212 };
214 ecam0: pci@848000000000 {
215 compatible = "pci-host-ecam-generic";
216 device_type = "pci";
217 msi-parent = <&its>;
218 msi-map = <0 &its 0 0x10000>;
219 bus-range = <0 31>;
220 #size-cells = <2>;
221 #address-cells = <3>;
222 #stream-id-cells = <1>;
223 u-boot,dm-pre-reloc;
224 dma-coherent;
225 reg = <0x8480 0x00000000 0 0x02000000>; /* Configuration space */
226 ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x080 0x00000000>, /* mem ranges */
227 <0x03000000 0x8100 0x00000000 0x8100 0x00000000 0x80 0x00000000>, /* SATA */
228 <0x03000000 0x8680 0x00000000 0x8680 0x00000000 0x160 0x28000000>, /* UARTs */
229 <0x03000000 0x87e0 0x2c000000 0x87e0 0x2c000000 0x000 0x94000000>, /* PEMs */
230 <0x03000000 0x8400 0x00000000 0x8400 0x00000000 0x010 0x00000000>, /* RNM */
231 <0x03000000 0x8430 0x00000000 0x8430 0x00000000 0x02 0x00000000>, /* NIC0*/
232 <0x03000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x01f 0x3a000000>;
234 mrml_bridge: mrml-bridge0@1,0 {
235 compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge";
236 #size-cells = <2>;
237 #address-cells = <3>;
238 ranges = <0x03000000 0x87e0 0x00000000 0x03000000 0x87e0 0x00000000 0x10 0x00000000>;
239 reg = <0x0800 0 0 0 0>; /* DEVFN = 0x08 (1:0) */
240 device_type = "pci";
241 u-boot,dm-pre-reloc;
243 mdio-nexus@1,3 {
244 compatible = "cavium,thunder-8890-mdio-nexus";
245 #address-cells = <2>;
246 #size-cells = <2>;
247 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
248 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
249 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
250 mdio0@87e005003800 {
251 compatible = "cavium,thunder-8890-mdio";
252 #address-cells = <1>;
253 #size-cells = <0>;
254 reg = <0x87e0 0x05003800 0x0 0x30>;
255 };
256 mdio1@87e005003880 {
257 compatible = "cavium,thunder-8890-mdio";
258 #address-cells = <1>;
259 #size-cells = <0>;
260 reg = <0x87e0 0x05003880 0x0 0x30>;
261 };
262 };
264 mmc_1_4: mmc@1,4 {
265 compatible = "cavium,thunder-8890-mmc";
266 reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */
267 #address-cells = <1>;
268 #size-cells = <0>;
269 clocks = <&sclk>;
270 };
272 i2c_9_0: i2c@9,0 {
273 #address-cells = <1>;
274 #size-cells = <0>;
275 compatible = "cavium,thunder-8890-twsi";
276 reg = <0x4800 0 0 0 0>; /* DEVFN = 0x48 (9:0) */
277 clock-frequency = <100000>;
278 clocks = <&sclk>;
279 u-boot,dm-pre-reloc;
280 };
282 i2c_9_1: i2c@9,1 {
283 #address-cells = <1>;
284 #size-cells = <0>;
285 compatible = "cavium,thunder-8890-twsi";
286 reg = <0x4900 0 0 0 0>; /* DEVFN = 0x49 (9:1) */
287 clock-frequency = <100000>;
288 clocks = <&sclk>;
289 u-boot,dm-pre-reloc;
290 };
292 rgx0 {
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "cavium,thunder-8890-bgx";
296 reg = <0x9000 0 0 0 0>; /* DEVFN = 0x90 (16:1) */
297 };
298 bgx0 {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 compatible = "cavium,thunder-8890-bgx";
302 reg = <0x8000 0 0 0 0>; /* DEVFN = 0x80 (16:0) */
303 };
304 bgx1 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "cavium,thunder-8890-bgx";
308 reg = <0x8100 0 0 0 0>; /* DEVFN = 0x81 (16:1) */
309 };
310 };
312 spi_7_0: spi@7,0 {
313 compatible = "cavium,thunder-8190-spi";
314 reg = <0x3800 0x0 0x0 0x0 0x0>; /* DEVFN = 0x38 (7:0) */
315 #address-cells = <1>;
316 #size-cells = <0>;
317 clocks = <&sclk>;
318 };
320 gpio_6_0: gpio0@6,0 {
321 #gpio-cells = <2>;
322 compatible = "cavium,thunder-8890-gpio";
323 gpio-controller;
324 reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */
325 u-boot,dm-pre-reloc;
326 };
328 nfc: nand@b,0 {
329 #address-cells = <1>;
330 #size-cells = <0>;
331 compatible = "cavium,cn8130-nand";
332 reg = <0x5800 0 0 0 0>; /* DEVFN = 0x58 (b:0) */
333 clocks = <&sclk>;
334 };
335 };
337 pem0: pci@87e0c0000000 {
339 /* "cavium,pci-host-thunder-pem" implies that
340 the first bus in bus-range has config access
341 via the "PEM space", subsequent buses have
342 config assess via the "Configuration space".
343 The "mem64 PEM" range is used to map the PEM
344 BAR0, which is used by the AER and PME MSI-X
345 sources. UEFI and Linux must assign the same
346 bus number to each device, otherwise Linux
347 enumeration gets confused. Because UEFI
348 skips the PEM bus and its PCIe-RC bridge it
349 uses a numbering that starts 1 bus higher.
350 */
352 compatible = "cavium,pci-host-thunder-pem";
353 device_type = "pci";
354 msi-parent = <&its>;
355 msi-map = <0 &its 0 0x10000>;
356 bus-range = <0x1f 0x57>;
357 #size-cells = <2>;
358 #address-cells = <3>;
359 #stream-id-cells = <1>;
360 dma-coherent;
361 reg = <0x8800 0x1f000000 0x0 0x39000000>, /* Configuration space */
362 <0x87e0 0xc0000000 0x0 0x01000000>; /* PEM space */
363 ranges = <0x01000000 0x00 0x00000000 0x8830 0x00000000 0x00 0x00010000>, /* I/O */
364 <0x03000000 0x00 0x10000000 0x8810 0x10000000 0x0f 0xf0000000>, /* mem64 */
365 <0x43000000 0x10 0x00000000 0x8820 0x00000000 0x10 0x00000000>, /* mem64-pref */
366 <0x03000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x00 0x01000000>; /* mem64 PEM */
368 #interrupt-cells = <1>;
369 interrupt-map-mask = <0 0 0 7>;
370 interrupt-map = <0 0 0 1 &gic0 0 0 0 16 4>, /* INTA */
371 <0 0 0 2 &gic0 0 0 0 17 4>, /* INTB */
372 <0 0 0 3 &gic0 0 0 0 18 4>, /* INTC */
373 <0 0 0 4 &gic0 0 0 0 19 4>; /* INTD */
374 };
376 pem1: pci@87e0c1000000 {
377 compatible = "cavium,pci-host-thunder-pem";
378 device_type = "pci";
379 msi-parent = <&its>;
380 msi-map = <0 &its 0 0x10000>;
381 bus-range = <0x57 0x8f>;
382 #size-cells = <2>;
383 #address-cells = <3>;
384 #stream-id-cells = <1>;
385 dma-coherent;
386 reg = <0x8840 0x57000000 0x0 0x39000000>, /* Configuration space */
387 <0x87e0 0xc1000000 0x0 0x01000000>; /* PEM space */
388 ranges = <0x01000000 0x00 0x00010000 0x8870 0x00010000 0x00 0x00010000>, /* I/O */
389 <0x03000000 0x00 0x10000000 0x8850 0x10000000 0x0f 0xf0000000>, /* mem64 */
390 <0x43000000 0x10 0x00000000 0x8860 0x00000000 0x10 0x00000000>, /* mem64-pref */
391 <0x03000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x00 0x01000000>; /* mem64 PEM */
393 #interrupt-cells = <1>;
394 interrupt-map-mask = <0 0 0 7>;
395 interrupt-map = <0 0 0 1 &gic0 0 0 0 20 4>, /* INTA */
396 <0 0 0 2 &gic0 0 0 0 21 4>, /* INTB */
397 <0 0 0 3 &gic0 0 0 0 22 4>, /* INTC */
398 <0 0 0 4 &gic0 0 0 0 23 4>; /* INTD */
399 };
401 pem2: pci@87e0c2000000 {
402 compatible = "cavium,pci-host-thunder-pem";
403 device_type = "pci";
404 msi-parent = <&its>;
405 msi-map = <0 &its 0 0x10000>;
406 bus-range = <0x8f 0xc7>;
407 #size-cells = <2>;
408 #address-cells = <3>;
409 #stream-id-cells = <1>;
410 dma-coherent;
411 reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */
412 <0x87e0 0xc2000000 0x0 0x01000000>; /* PEM space */
413 ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */
414 <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */
415 <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */
416 <0x03000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x00 0x01000000>; /* mem64 PEM */
418 #interrupt-cells = <1>;
419 interrupt-map-mask = <0 0 0 7>;
420 interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */
421 <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */
422 <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */
423 <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */
424 };
426 tdm: tdm@d,0 {
427 #address-cells = <1>;
428 #size-cells = <0>;
429 compatible = "cavium,thunder-8190-tdm";
430 reg = <0x6800 0 0 0>; /* DEVFN = 0x68 (d:0) */
431 clocks = <&sclk>;
432 };
433 };
435 aliases {
436 serial0 = &uaa0;
437 serial1 = &uaa1;
438 serial2 = &uaa2;
439 serial3 = &uaa3;
440 i2c0 = &i2c_9_0;
441 i2c1 = &i2c_9_1;
442 spi0 = &spi_7_0;
443 };
445 chosen {
446 stdout-path = "serial0:115200n8";
447 };
450 memory@0 {
451 device_type = "memory";
452 reg = <0x0 0x01400000 0x0 0x7EC00000>;
453 /* socket 0 */
454 numa-node-id = <0>;
455 };
456 };