| blob | 2566b2d9f9cd5ebd50603e312282ca3a468a37ef |
1 /* SPDX-License-Identifier: BSD-3-Clause */
3 / {
4 cavium,bdk {
5 /* Speed grade to use for DRAM in MT/s. Hardware may adjust this value
6 slightly to improve DRAM stability, so scope measurements may not
7 exactly match the frequency with MT/s. The Cavium supported speed
8 grades are:
9 0 (auto-set from SPD contents)
10 666 MT/s (DDR3 only)
11 800 MT/s (DDR3 only)
12 1066 MT/s (DDR3 only)
13 1333 MT/s (DDR3 only)
14 1600 MT/s
15 1866 MT/s
16 2133 MT/s (DDR4 only)
17 Parameters:
18 N#: Parameter can be different for each node. This specifies
19 which node the value is for. Node must be 0-3. Optional. */
20 //DDR-SPEED.N%d = "0";
22 /* Set to use a an alternate reference clock for DRAM than the usual
23 50Mhz reference. The value of here specifies the frequency of the
24 alternate clock in Mhz. Currently the only supported reference
25 clock frequencies are 50Mhz and 100Mhz.
26 Parameters:
27 N#: Parameter can be different for each node. This specifies
28 which node the value is for. Node must be 0-3. Optional. */
29 //DDR-ALT-REFCLK.N%d = "0";
31 /* TWSI address of the DIMM SPD. The encoding of this address is
32 : [15:12]: TWSI bus the DIMM is connected to.
33 [11:7]: Reserved, set to zero.
34 [6:0]: TWSI address for the DIMM.
35 A value of zero means the DIMMs are not accessible. Hard coded
36 values will be read from DDR-CONFIG-SPD-DATA.Parameters:
37 LMC#: Parameter can be different for memory controller. This
38 specifies which LMC the value is for. LMC must be
39 0-3. Optional.
40 N#: Parameter can be different for each node. This specifies
41 which node the value is for. Node must be 0-3. Optional. */
42 //DDR-CONFIG-SPD-ADDR.DIMM%d.LMC%d.N%d = "0";
43 // Note: The SPD addresses are not specified here so boards don't
44 // inherit a default. The default causes trouble with UEFI when it
45 // builds SMBIOS tables.
47 /* DIMM SPD data to be used if memory doesn't support the standard
48 TWSI access to DIMM SPDs. The format of this is a binary blob
49 stored in the device tree. An example would be:
50 Parameters:
51 LMC#: Parameter can be different for memory controller. This
52 specifies which LMC the value is for. LMC must be
53 0-3. Optional.
54 N#: Parameter can be different for each node. This specifies
55 which node the value is for. Node must be 0-3. Optional. */
56 //DDR-CONFIG-SPD-DATA.DIMM%d.LMC%d.N%d = [];
58 /* Drive strength control for DDR_DQ* / DDR_DQS_*_P/N drivers.
59 0x1 = 24 ohm.
60 0x2 = 26.67 ohm.
61 0x3 = 30 ohm.
62 0x4 = 34.3 ohm.
63 0x5 = 40 ohm.
64 0x6 = 48 ohm.
65 0x7 = 60 ohm.
66 _ else = Reserved.
67 Parameters:
68 RANKS#: Specifies that this parameter only applies to DIMMs
69 with the supplied number of ranks. Support ranks is 1, 2,
70 or 4. Optional.
71 DIMMS#: Specifies that this parameter only applies when the
72 DIMMs per memory controller matches. Support number of
73 DIMMs is 1 or 2. Optional.
74 LMC#: Parameter can be different for memory controller. This
75 specifies which LMC the value is for. LMC must be
76 0-3. Optional.
77 N#: Parameter can be different for each node. This specifies
78 which node the value is for. Node must be 0-3. Optional. */
79 //DDR-CONFIG-DQX-CTL.RANKS%d.DIMMS%d.LMC%d.N%d = "0";
80 DDR-CONFIG-DQX-CTL = "0x4";
82 /* LMC Write OnDieTermination Mask Register
83 System designers may desire to terminate DQ/DQS lines for
84 higher-frequency DDR operations, especially on a multirank system.
85 DDR3 DQ/DQS I/Os have built-in termination resistors that can be
86 turned on or off by the controller, after meeting TAOND and TAOF
87 timing requirements. Each rank has its own ODT pin that fans out
88 to all of the memory parts in that DIMM. System designers may
89 prefer different combinations of ODT ONs for write operations into
90 different ranks. CNXXXX supports full programmability by way of
91 the mask register below. Each rank position has its own 8-bit
92 programmable field. When the controller does a write to that rank,
93 it sets the 4 ODT pins to the mask pins below. For example, when
94 doing a write into Rank0, a system designer may desire to terminate
95 the lines with the resistor on DIMM0/Rank1. The mask WODT_D0_R0
96 would then be {00000010}.
97 CNXXXX drives the appropriate mask values on the ODT pins by
98 default. If this feature is not required, write 0x0 in this
99 register. When a given RANK is selected, the WODT mask for that
100 RANK is used.
101 Parameters:
102 RANKS#: Specifies that this parameter only applies to DIMMs
103 with the supplied number of ranks. Support ranks is 1, 2,
104 or 4. Optional.
105 DIMMS#: Specifies that this parameter only applies when the
106 DIMMs per memory controller matches. Support number of
107 DIMMs is 1 or 2. Optional.
108 LMC#: Parameter can be different for memory controller. This
109 specifies which LMC the value is for. LMC must be
110 0-3. Optional.
111 N#: Parameter can be different for each node. This specifies
112 which node the value is for. Node must be 0-3. Optional. */
113 //DDR-CONFIG-WODT-MASK.RANKS%d.DIMMS%d.LMC%d.N%d = "0";
114 DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2 = "0xc0c0303";
115 DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1 = "0x1030203";
117 /* Partial array self-refresh per rank. LMC writes this value to
118 MR2[PASR] in the rank (i.e. DIMM0_CS0) DDR3 parts when selected
119 during power-up/init, write-leveling, and, if
120 LMC()_CONFIG[SREF_WITH_DLL] is set, self-refresh entry and exit
121 instruction sequences. See LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and
122 LMC()_CONFIG[RANKMASK] and LMC()_RESET_CTL[DDR3PWARM,DDR3PSOFT].
123 Parameters:
124 RANKS#: Specifies that this parameter only applies to DIMMs
125 with the supplied number of ranks. Support ranks is 1, 2,
126 or 4. Optional.
127 DIMMS#: Specifies that this parameter only applies when the
128 DIMMs per memory controller matches. Support number of
129 DIMMs is 1 or 2. Optional.
130 RANK#: Parameter can be different for each rank of a DIMM. This
131 specifies which rank the value is for. Rank must be
132 0-3. Optional.
133 LMC#: Parameter can be different for memory controller. This
134 specifies which LMC the value is for. LMC must be
135 0-3. Optional.
136 N#: Parameter can be different for each node. This specifies
137 which node the value is for. Node must be 0-3. Optional. */
138 //DDR-CONFIG-MODE1-PASR.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0";
140 /* Auto self-refresh per rank. LMC writes this value to MR2[ASR] in
141 the rank (i.e. DIMM0_CS0) DDR3 parts when selected during
142 power-up/init, write-leveling, and, if LMC()_CONFIG[SREF_WITH_DLL]
143 is set, self-refresh entry and exit instruction sequences. See
144 LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and LMC()_CONFIG[RANKMASK] and
145 LMC()_RESET_CTL [DDR3PWARM,DDR3PSOFT].
146 Parameters:
147 RANKS#: Specifies that this parameter only applies to DIMMs
148 with the supplied number of ranks. Support ranks is 1, 2,
149 or 4. Optional.
150 DIMMS#: Specifies that this parameter only applies when the
151 DIMMs per memory controller matches. Support number of
152 DIMMs is 1 or 2. Optional.
153 RANK#: Parameter can be different for each rank of a DIMM. This
154 specifies which rank the value is for. Rank must be
155 0-3. Optional.
156 LMC#: Parameter can be different for memory controller. This
157 specifies which LMC the value is for. LMC must be
158 0-3. Optional.
159 N#: Parameter can be different for each node. This specifies
160 which node the value is for. Node must be 0-3. Optional. */
161 //DDR-CONFIG-MODE1-ASR.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0";
163 /* Self-refresh temperature range per rank. LMC writes this value to
164 MR2[SRT] in the rank (i.e. DIMM0_CS0) DDR3 parts when selected
165 during power-up/init, write-leveling, and, if
166 LMC()_CONFIG[SREF_WITH_DLL] is set, self-refresh entry and exit
167 instruction sequences. See LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and
168 LMC()_CONFIG[RANKMASK] and LMC()_RESET_CTL[DDR3PWARM,DDR3PSOFT].
169 Parameters:
170 RANKS#: Specifies that this parameter only applies to DIMMs
171 with the supplied number of ranks. Support ranks is 1, 2,
172 or 4. Optional.
173 DIMMS#: Specifies that this parameter only applies when the
174 DIMMs per memory controller matches. Support number of
175 DIMMs is 1 or 2. Optional.
176 RANK#: Parameter can be different for each rank of a DIMM. This
177 specifies which rank the value is for. Rank must be
178 0-3. Optional.
179 LMC#: Parameter can be different for memory controller. This
180 specifies which LMC the value is for. LMC must be
181 0-3. Optional.
182 N#: Parameter can be different for each node. This specifies
183 which node the value is for. Node must be 0-3. Optional. */
184 //DDR-CONFIG-MODE1-SRT.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0";
186 /* RTT_WR per rank. LMC writes this value to MR2[RTT_WR] in the rank
187 (i.e. DIMM0_CS0) DDR3 parts when selected during power-up/init,
188 write-leveling, and, if LMC()_CONFIG[SREF_WITH_DLL] is set,
189 self-refresh entry and exit instruction sequences. See
190 LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and LMC()_CONFIG[RANKMASK] and
191 LMC()_RESET_CTL[DDR3PWARM, DDR3PSOFT].
192 Parameters:
193 RANKS#: Specifies that this parameter only applies to DIMMs
194 with the supplied number of ranks. Support ranks is 1, 2,
195 or 4. Optional.
196 DIMMS#: Specifies that this parameter only applies when the
197 DIMMs per memory controller matches. Support number of
198 DIMMs is 1 or 2. Optional.
199 RANK#: Parameter can be different for each rank of a DIMM. This
200 specifies which rank the value is for. Rank must be
201 0-3. Optional.
202 LMC#: Parameter can be different for memory controller. This
203 specifies which LMC the value is for. LMC must be
204 0-3. Optional.
205 N#: Parameter can be different for each node. This specifies
206 which node the value is for. Node must be 0-3. Optional. */
207 //DDR-CONFIG-MODE1-RTT-WR.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0";
209 //DDR-CONFIG-MODE1-RTT-WR.RANKS1 = "0x4";
210 DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS1.RANK0 = "0x4";
211 DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK0 = "0x4";
212 DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK2 = "0x4";
214 //DDR-CONFIG-MODE1-RTT-WR.RANKS2 = "0x2";
215 DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK0 = "0x2";
216 DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK1 = "0x2";
217 DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS2 = "0x2";
219 DDR-CONFIG-MODE1-RTT-WR.RANKS4 = "0x1";
221 /* Output driver impedance control per rank. LMC writes this value
222 to MR1[D.I.C.] in the rank (i.e. DIMM0_CS0) DDR3 parts when
223 selected during power-up/init, write-leveling, and, if
224 LMC()_CONFIG[SREF_WITH_DLL] is set, self-refresh entry and exit
225 instruction sequences. See LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and
226 LMC()_CONFIG[RANKMASK] and LMC()_RESET_CTL[DDR3PWARM,DDR3PSOFT].
227 Parameters:
228 RANKS#: Specifies that this parameter only applies to DIMMs
229 with the supplied number of ranks. Support ranks is 1, 2,
230 or 4. Optional.
231 DIMMS#: Specifies that this parameter only applies when the
232 DIMMs per memory controller matches. Support number of
233 DIMMs is 1 or 2. Optional.
234 RANK#: Parameter can be different for each rank of a DIMM. This
235 specifies which rank the value is for. Rank must be
236 0-3. Optional.
237 LMC#: Parameter can be different for memory controller. This
238 specifies which LMC the value is for. LMC must be
239 0-3. Optional.
240 N#: Parameter can be different for each node. This specifies
241 which node the value is for. Node must be 0-3. Optional. */
242 //DDR-CONFIG-MODE1-DIC.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0";
243 DDR-CONFIG-MODE1-DIC.RANKS4.DIMMS1 = "0x1";
245 /* RTT_NOM per rank. LMC writes this value to MR1[RTT_NOM] in the
246 rank (i.e. DIMM0_CS0) DDR3 parts when selected during
247 power-up/init, write-leveling, and, if LMC()_CONFIG[SREF_WITH_DLL]
248 is set, self-refresh entry and exit instruction sequences. See
249 LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and LMC()_CONFIG[RANKMASK] and
250 LMC()_RESET_CTL[DDR3PWARM, DDR3PSOFT]. Per JEDEC DDR3
251 specifications, if RTT_NOM is used during write operations, only
252 values MR1[RTT_NOM] = 1 (RZQ/4), 2 (RZQ/2), or 3 (RZQ/6) are
253 allowed. Otherwise, values MR1[RTT_NOM] = 4 (RZQ/12) and 5 (RZQ/8)
254 are also allowed.
255 Parameters:
256 RANKS#: Specifies that this parameter only applies to DIMMs
257 with the supplied number of ranks. Support ranks is 1, 2,
258 or 4. Optional.
259 DIMMS#: Specifies that this parameter only applies when the
260 DIMMs per memory controller matches. Support number of
261 DIMMs is 1 or 2. Optional.
262 RANK#: Parameter can be different for each rank of a DIMM. This
263 specifies which rank the value is for. Rank must be
264 0-3. Optional.
265 LMC#: Parameter can be different for memory controller. This
266 specifies which LMC the value is for. LMC must be
267 0-3. Optional.
268 N#: Parameter can be different for each node. This specifies
269 which node the value is for. Node must be 0-3. Optional. */
270 //DDR-CONFIG-MODE1-RTT-NOM.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0";
271 DDR-CONFIG-MODE1-RTT-NOM.RANKS2.DIMMS2 = "0x2";
272 DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK0 = "0x4";
273 DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK2 = "0x4";
275 /* Host Interface DQ/DQS Output Driver Impedance control for DIMM0's
276 Data Buffer. This is the default value used during Host Interface
277 Write Leveling in LRDIMM environment, i.e.,
278 LMC()_CONFIG[LRDIMM_ENA] = 1, LMC()_SEQ_CTL[SEQ_SEL] = 0x6.
279 0x0 = RZQ/6 (40 ohm).
280 0x1 = RZQ/7 (34 ohm).
281 0x2 = RZQ/5 (48 ohm).
282 0x3-0x7 = Reserved.
283 Parameters:
284 RANKS#: Specifies that this parameter only applies to DIMMs
285 with the supplied number of ranks. Support ranks is 1, 2,
286 or 4. Optional.
287 DIMMS#: Specifies that this parameter only applies when the
288 DIMMs per memory controller matches. Support number of
289 DIMMs is 1 or 2. Optional.
290 LMC#: Parameter can be different for memory controller. This
291 specifies which LMC the value is for. LMC must be
292 0-3. Optional.
293 N#: Parameter can be different for each node. This specifies
294 which node the value is for. Node must be 0-3. Optional. */
295 //DDR-CONFIG-MODE1-DB-OUTPUT-IMPEDANCE.RANKS%d.DIMMS%d.LMC%d.N%d = "0";
297 /* RTT park value per rank.
298 Parameters:
299 RANKS#: Specifies that this parameter only applies to DIMMs
300 with the supplied number of ranks. Support ranks is 1, 2,
301 or 4. Optional.
302 DIMMS#: Specifies that this parameter only applies when the
303 DIMMs per memory controller matches. Support number of
304 DIMMs is 1 or 2. Optional.
305 RANK#: Parameter can be different for each rank of a DIMM. This
306 specifies which rank the value is for. Rank must be
307 0-3. Optional.
308 LMC#: Parameter can be different for memory controller. This
309 specifies which LMC the value is for. LMC must be
310 0-3. Optional.
311 N#: Parameter can be different for each node. This specifies
312 which node the value is for. Node must be 0-3. Optional. */
313 //DDR-CONFIG-MODE2-RTT-PARK.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0";
315 //DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1 = "0x1";
316 DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1.RANK0 = "0x1";
318 //DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2 = "0x5";
319 DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK0 = "0x5";
320 DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK2 = "0x5";
322 //DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1 = "0x2";
323 DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK0 = "0x2";
324 DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK1 = "0x2";
326 DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS2 = "0x1";
327 DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK0 = "0x6";
328 DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK1 = "0x6";
330 /* VREF value per rank.
331 Parameters:
332 RANKS#: Specifies that this parameter only applies to DIMMs
333 with the supplied number of ranks. Support ranks is 1, 2,
334 or 4. Optional.
335 DIMMS#: Specifies that this parameter only applies when the
336 DIMMs per memory controller matches. Support number of
337 DIMMs is 1 or 2. Optional.
338 RANK#: Parameter can be different for each rank of a DIMM. This
339 specifies which rank the value is for. Rank must be
340 0-3. Optional.
341 LMC#: Parameter can be different for memory controller. This
342 specifies which LMC the value is for. LMC must be
343 0-3. Optional.
344 N#: Parameter can be different for each node. This specifies
345 which node the value is for. Node must be 0-3. Optional. */
346 //DDR-CONFIG-MODE2-VREF-VALUE.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0";
348 //DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1 = "0x22";
349 DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1.RANK0 = "0x22";
351 //DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2 = "0x1f";
352 DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK0 = "0x1f";
353 DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK2 = "0x1f";
355 //DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1 = "0x19";
356 DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK0 = "0x19";
357 DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK1 = "0x19";
359 DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS2 = "0x19";
360 DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK0 = "0x1f";
361 DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK1 = "0x1f";
363 /* VREF range per rank.
364 Parameters:
365 RANKS#: Specifies that this parameter only applies to DIMMs
366 with the supplied number of ranks. Support ranks is 1, 2,
367 or 4. Optional.
368 DIMMS#: Specifies that this parameter only applies when the
369 DIMMs per memory controller matches. Support number of
370 DIMMs is 1 or 2. Optional.
371 RANK#: Parameter can be different for each rank of a DIMM. This
372 specifies which rank the value is for. Rank must be
373 0-3. Optional.
374 LMC#: Parameter can be different for memory controller. This
375 specifies which LMC the value is for. LMC must be
376 0-3. Optional.
377 N#: Parameter can be different for each node. This specifies
378 which node the value is for. Node must be 0-3. Optional. */
379 //DDR-CONFIG-MODE2-VREF-RANGE.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0";
381 /* Vref training mode enable, used for all ranks.
382 Parameters:
383 RANKS#: Specifies that this parameter only applies to DIMMs
384 with the supplied number of ranks. Support ranks is 1, 2,
385 or 4. Optional.
386 DIMMS#: Specifies that this parameter only applies when the
387 DIMMs per memory controller matches. Support number of
388 DIMMs is 1 or 2. Optional.
389 LMC#: Parameter can be different for memory controller. This
390 specifies which LMC the value is for. LMC must be
391 0-3. Optional.
392 N#: Parameter can be different for each node. This specifies
393 which node the value is for. Node must be 0-3. Optional. */
394 //DDR-CONFIG-MODE2-VREFDQ-TRAIN-EN.RANKS%d.DIMMS%d.LMC%d.N%d = "0";
396 /* RODT NCTL impedance control bits. This field controls ODT values
397 during a memory read.
398 0x0 = No ODT.
399 0x1 = 20 ohm.
400 0x2 = 30 ohm.
401 0x3 = 40 ohm.
402 0x4 = 60 ohm.
403 0x5 = 120 ohm.
404 _ else = Reserved.
405 In DDR4 mode:
406 0x0 = No ODT.
407 0x1 = 40 ohm.
408 0x2 = 60 ohm.
409 0x3 = 80 ohm.
410 0x4 = 120 ohm.
411 0x5 = 240 ohm.
412 0x6 = 34 ohm.
413 0x7 = 48 ohm.
414 _ else = Reserved.
415 Parameters:
416 RANKS#: Specifies that this parameter only applies to DIMMs
417 with the supplied number of ranks. Support ranks is 1, 2,
418 or 4. Optional.
419 DIMMS#: Specifies that this parameter only applies when the
420 DIMMs per memory controller matches. Support number of
421 DIMMs is 1 or 2. Optional.
422 LMC#: Parameter can be different for memory controller. This
423 specifies which LMC the value is for. LMC must be
424 0-3. Optional.
425 N#: Parameter can be different for each node. This specifies
426 which node the value is for. Node must be 0-3. Optional. */
427 //DDR-CONFIG-RODT-CTL.RANKS%d.DIMMS%d.LMC%d.N%d = "0";
428 DDR-CONFIG-RODT-CTL.RANKS1.DIMMS1 = "0x7";
429 DDR-CONFIG-RODT-CTL.RANKS1.DIMMS2 = "0x3";
430 DDR-CONFIG-RODT-CTL.RANKS2.DIMMS1 = "0x3";
431 DDR-CONFIG-RODT-CTL.RANKS2.DIMMS2 = "0x7";
432 DDR-CONFIG-RODT-CTL.RANKS4.DIMMS1 = "0x7";
434 /* LMC Read OnDieTermination Mask Register
435 System designers may desire to terminate DQ/DQS lines for higher
436 frequency DDR operations, especially on a multirank system. DDR3
437 DQ/DQS I/Os have built-in termination resistors that can be turned
438 on or off by the controller, after meeting TAOND and TAOF timing
439 requirements.
440 Each rank has its own ODT pin that fans out to all the memory
441 parts in that DIMM. System designers may prefer different
442 combinations of ODT ONs for read operations into different ranks.
443 CNXXXX supports full programmability by way of the mask register
444 below. Each rank position has its own 4-bit programmable field.
445 When the controller does a read to that rank, it sets the 4 ODT
446 pins to the MASK pins below. For example, when doing a read from
447 Rank0, a system designer may desire to terminate the lines with
448 the resistor on DIMM0/Rank1. The mask RODT_D0_R0 would then be {0010}.
449 CNXXXX drives the appropriate mask values on the ODT pins by
450 default. If this feature is not required, write 0x0 in this
451 register. Note that, as per the JEDEC DDR3 specifications, the ODT
452 pin for the rank that is being read should always be 0x0. When a
453 given RANK is selected, the RODT mask for that rank is used.
454 Parameters:
455 RANKS#: Specifies that this parameter only applies to DIMMs
456 with the supplied number of ranks. Support ranks is 1, 2,
457 or 4. Optional.
458 DIMMS#: Specifies that this parameter only applies when the
459 DIMMs per memory controller matches. Support number of
460 DIMMs is 1 or 2. Optional.
461 LMC#: Parameter can be different for memory controller. This
462 specifies which LMC the value is for. LMC must be
463 0-3. Optional.
464 N#: Parameter can be different for each node. This specifies
465 which node the value is for. Node must be 0-3. Optional. */
466 //DDR-CONFIG-RODT-MASK.RANKS%d.DIMMS%d.LMC%d.N%d = "0";
467 DDR-CONFIG-RODT-MASK.RANKS2.DIMMS2 = "0x4080102";
468 DDR-CONFIG-RODT-MASK.RANKS4.DIMMS1 = "0x1010202";
470 /* 1=120ohms, 2=60ohms, 3=40ohms, 4=30ohms, 5=20ohms
471 Parameters:
472 LMC#: Parameter can be different for memory controller. This
473 specifies which LMC the value is for. LMC must be
474 0-3. Optional.
475 N#: Parameter can be different for each node. This specifies
476 which node the value is for. Node must be 0-3. Optional. */
477 //DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX.LMC%d.N%d = "1";
478 DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX = "0x1";
480 /* 1=120ohms, 2=60ohms, 3=40ohms, 4=30ohms, 5=20ohms
481 Parameters:
482 LMC#: Parameter can be different for memory controller. This
483 specifies which LMC the value is for. LMC must be
484 0-3. Optional.
485 N#: Parameter can be different for each node. This specifies
486 which node the value is for. Node must be 0-3. Optional. */
487 //DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX.LMC%d.N%d = "5";
488 DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX = "0x7";
490 /* 1=20ohms, 2=30ohms, 3=40ohms, 4=60ohms, 5=120ohms
491 Parameters:
492 LMC#: Parameter can be different for memory controller. This
493 specifies which LMC the value is for. LMC must be
494 0-3. Optional.
495 N#: Parameter can be different for each node. This specifies
496 which node the value is for. Node must be 0-3. Optional. */
497 //DDR-CONFIG-CUSTOM-MIN-RODT-CTL.LMC%d.N%d = "1";
498 DDR-CONFIG-CUSTOM-MIN-RODT-CTL = "0x1";
500 /* 1=20ohms, 2=30ohms, 3=40ohms, 4=60ohms, 5=120ohms
501 Parameters:
502 LMC#: Parameter can be different for memory controller. This
503 specifies which LMC the value is for. LMC must be
504 0-3. Optional.
505 N#: Parameter can be different for each node. This specifies
506 which node the value is for. Node must be 0-3. Optional. */
507 //DDR-CONFIG-CUSTOM-MAX-RODT-CTL.LMC%d.N%d = "5";
508 DDR-CONFIG-CUSTOM-MAX-RODT-CTL = "0x7";
510 /* Drive strength control for DDR_CK_X_P, DDR_DIMMX_CSX_L,
511 DDR_DIMMX_ODT_X drivers.
512 Parameters:
513 LMC#: Parameter can be different for memory controller. This
514 specifies which LMC the value is for. LMC must be
515 0-3. Optional.
516 N#: Parameter can be different for each node. This specifies
517 which node the value is for. Node must be 0-3. Optional. */
518 //DDR-CONFIG-CUSTOM-CK-CTL.LMC%d.N%d = "0";
519 DDR-CONFIG-CUSTOM-CK-CTL = "0x4";
521 /* Drive strength control for CMD/A/RESET_L/CKEX drivers.
522 Parameters:
523 LMC#: Parameter can be different for memory controller. This
524 specifies which LMC the value is for. LMC must be
525 0-3. Optional.
526 N#: Parameter can be different for each node. This specifies
527 which node the value is for. Node must be 0-3. Optional. */
528 //DDR-CONFIG-CUSTOM-CMD-CTL.LMC%d.N%d = "0";
529 DDR-CONFIG-CUSTOM-CMD-CTL = "0x4";
531 /* Drive strength control for ODT, etc. drivers.
532 In DDR3 mode:
533 0x1 = 24 ohm.
534 0x2 = 26.67 ohm.
535 0x3 = 30 ohm.
536 0x4 = 34.3 ohm.
537 0x5 = 40 ohm.
538 0x6 = 48 ohm.
539 0x7 = 60 ohm.
540 else = Reserved.
541 In DDR4 mode:
542 0x0 = Reserved.
543 0x1 = Reserved.
544 0x2 = 26 ohm.
545 0x3 = 30 ohm.
546 0x4 = 34 ohm.
547 0x5 = 40 ohm.
548 0x6 = 48 ohm.
549 else = Reserved.
550 Parameters:
551 LMC#: Parameter can be different for memory controller. This
552 specifies which LMC the value is for. LMC must be
553 0-3. Optional.
554 N#: Parameter can be different for each node. This specifies
555 which node the value is for. Node must be 0-3. Optional. */
556 //DDR-CONFIG-CUSTOM-CTL-CTL.LMC%d.N%d = "0";
557 DDR-CONFIG-CUSTOM-CTL-CTL = "0x4";
559 /* Minimum allowed CAS Latency
560 Parameters:
561 LMC#: Parameter can be different for memory controller. This
562 specifies which LMC the value is for. LMC must be
563 0-3. Optional.
564 N#: Parameter can be different for each node. This specifies
565 which node the value is for. Node must be 0-3. Optional. */
566 //DDR-CONFIG-CUSTOM-MIN-CAS-LATENCY.LMC%d.N%d = "0";
568 /* When set, LMC attempts to select the read-leveling setting that is
569 LMC()_RLEVEL_CTL[OFFSET] settings earlier than the last passing
570 read-leveling setting in the largest contiguous sequence of
571 passing settings. When clear, or if the setting selected by
572 LMC()_RLEVEL_CTL[OFFSET] did not pass, LMC selects the middle
573 setting in the largest contiguous sequence of passing settings,
574 rounding earlier when necessary.
575 Parameters:
576 LMC#: Parameter can be different for memory controller. This
577 specifies which LMC the value is for. LMC must be
578 0-3. Optional.
579 N#: Parameter can be different for each node. This specifies
580 which node the value is for. Node must be 0-3. Optional. */
581 //DDR-CONFIG-CUSTOM-OFFSET-EN.LMC%d.N%d = "1";
582 DDR-CONFIG-CUSTOM-OFFSET-EN = "0x1";
584 /* The offset used when LMC()_RLEVEL_CTL[OFFSET] is set.
585 Parameters:
586 %s: This setting can by specified by DRAM type (UDIMM or RDIMM)
587 Different settings can be used for each, or the type can be
588 omitted to use the same setting for both.
589 LMC#: Parameter can be different for memory controller. This
590 specifies which LMC the value is for. LMC must be
591 0-3. Optional.
592 N#: Parameter can be different for each node. This specifies
593 which node the value is for. Node must be 0-3. Optional. */
594 //DDR-CONFIG-CUSTOM-OFFSET.%s.LMC%d.N%d = "0";
595 DDR-CONFIG-CUSTOM-OFFSET = "0x2";
597 /* Enables software interpretation of per-byte read delays using the
598 measurements collected by the chip rather than completely relying
599 on the automatically to determine the delays. 1=software
600 computation is recommended since a more complete analysis is
601 implemented in software.
602 Parameters:
603 LMC#: Parameter can be different for memory controller. This
604 specifies which LMC the value is for. LMC must be
605 0-3. Optional.
606 N#: Parameter can be different for each node. This specifies
607 which node the value is for. Node must be 0-3. Optional. */
608 //DDR-CONFIG-CUSTOM-RLEVEL-COMPUTE.LMC%d.N%d = "0";
610 /* Set to 2 unless instructed differently by Cavium.
611 Parameters:
612 LMC#: Parameter can be different for memory controller. This
613 specifies which LMC the value is for. LMC must be
614 0-3. Optional.
615 N#: Parameter can be different for each node. This specifies
616 which node the value is for. Node must be 0-3. Optional. */
617 //DDR-CONFIG-CUSTOM-RLEVEL-COMP-OFFSET.%s.LMC%d.N%d = "2";
619 /* Turn on the DDR 2T mode. 2-cycle window for CMD and address. This
620 mode helps relieve setup time pressure on the address and command
621 bus. Please refer to Micron's tech note tn_47_01 titled DDR2-533
622 Memory Design Guide for Two DIMM Unbuffered Systems for physical
623 details.
624 Parameters:
625 %s: This setting can by specified by DRAM type (UDIMM or RDIMM)
626 Different settings can be used for each, or the type can be
627 omitted to use the same setting for both.
628 LMC#: Parameter can be different for memory controller. This
629 specifies which LMC the value is for. LMC must be
630 0-3. Optional.
631 N#: Parameter can be different for each node. This specifies
632 which node the value is for. Node must be 0-3. Optional. */
633 //DDR-CONFIG-CUSTOM-DDR2T.%s.LMC%d.N%d = "0";
634 DDR-CONFIG-CUSTOM-DDR2T = "0x1";
636 /* As result of the flyby topology prescribed in the JEDEC
637 specifications the byte delays should maintain a consistent
638 increasing or decreasing trend across the bytes on standard DIMMs.
639 This setting can be used disable that check for unusual
640 circumstances where the check is not useful.
641 Parameters:
642 LMC#: Parameter can be different for memory controller. This
643 specifies which LMC the value is for. LMC must be
644 0-3. Optional.
645 N#: Parameter can be different for each node. This specifies
646 which node the value is for. Node must be 0-3. Optional. */
647 //DDR-CONFIG-CUSTOM-DISABLE-SEQUENTIAL-DELAY-CHECK.LMC%d.N%d = "0";
649 /* An additional sequential delay check for the delays that result
650 from the flyby topology. This value specifies the maximum
651 difference between the delays of adjacent bytes. A value of 0
652 disables this check.
653 Parameters:
654 LMC#: Parameter can be different for memory controller. This
655 specifies which LMC the value is for. LMC must be
656 0-3. Optional.
657 N#: Parameter can be different for each node. This specifies
658 which node the value is for. Node must be 0-3. Optional. */
659 //DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT.LMC%d.N%d = "0";
660 DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT = "0x2";
662 /* The parity input signal PAR_IN on each DIMM must be strapped high
663 or low on the board. This bit is programmed into
664 LMC0_DIMM_CTL[PARITY] and it must be set to match the board
665 strapping. This signal is typically strapped low.
666 Parameters:
667 LMC#: Parameter can be different for memory controller. This
668 specifies which LMC the value is for. LMC must be
669 0-3. Optional.
670 N#: Parameter can be different for each node. This specifies
671 which node the value is for. Node must be 0-3. Optional. */
672 //DDR-CONFIG-CUSTOM-PARITY.LMC%d.N%d = "0";
674 /* Front Porch Enable: When set, the turn-off time for the default
675 DDR_DQ/DQS drivers is FPRCH2 CKs earlier.
676 0 = 0 CKs
677 1 = 1 CKs
678 2 = 2 CKs
679 Parameters:
680 LMC#: Parameter can be different for memory controller. This
681 specifies which LMC the value is for. LMC must be
682 0-3. Optional.
683 N#: Parameter can be different for each node. This specifies
684 which node the value is for. Node must be 0-3. Optional. */
685 //DDR-CONFIG-CUSTOM-FPRCH2.LMC%d.N%d = "0";
686 DDR-CONFIG-CUSTOM-FPRCH2 = "0x2";
688 /* Enable 32-bit datapath mode. Set to 1 if only 32 DQ pins are
689 used.
690 Parameters:
691 LMC#: Parameter can be different for memory controller. This
692 specifies which LMC the value is for. LMC must be
693 0-3. Optional.
694 N#: Parameter can be different for each node. This specifies
695 which node the value is for. Node must be 0-3. Optional. */
696 //DDR-CONFIG-CUSTOM-MODE32B.LMC%d.N%d = "0";
698 /* Use Measured VREF
699 Parameters:
700 LMC#: Parameter can be different for memory controller. This
701 specifies which LMC the value is for. LMC must be
702 0-3. Optional.
703 N#: Parameter can be different for each node. This specifies
704 which node the value is for. Node must be 0-3. Optional. */
705 //DDR-CONFIG-CUSTOM-MEASURED-VREF.LMC%d.N%d = "0";
707 /* Supply a custom DLL write offset
708 Parameters:
709 BYTE#: Byte lane to apply the parameter to (0-8).
710 LMC#: Parameter can be different for memory controller. This
711 specifies which LMC the value is for. LMC must be
712 0-3. Optional.
713 N#: Parameter can be different for each node. This specifies
714 which node the value is for. Node must be 0-3. Optional. */
715 //DDR-CONFIG-CUSTOM-DLL-WRITE-OFFSET.BYTE%d.LMC%d.N%d = "0";
717 /* Supply a custom DLL read offset
718 Parameters:
719 BYTE#: Byte lane to apply the parameter to (0-8).
720 LMC#: Parameter can be different for memory controller. This
721 specifies which LMC the value is for. LMC must be
722 0-3. Optional.
723 N#: Parameter can be different for each node. This specifies
724 which node the value is for. Node must be 0-3. Optional. */
725 //DDR-CONFIG-CUSTOM-DLL-READ-OFFSET.BYTE%d.LMC%d.N%d = "0";
727 /* Choose the debug logging level used during DRAM initialization.
728 Zero disables debug logging. The possible debug levels are:
729 0: Off, no logging
730 1: Logging of DRAM initialization at a normal detail level
731 2: Logging of DRAM initialization at FAE detail level
732 3: Logging of DRAM initialization at TME detail level
733 4: Logging of DRAM initialization at DEV detail level
734 5: Logging of DRAM initialization at DEV2 detail level
735 6: Logging of DRAM initialization at DEV3 detail level
736 7: Logging of DRAM initialization at DEV4 detail level
737 Add in the following for special trace features.
738 16: Trace specialized DRAM controller sequences.
739 32: Trace every DRAM controller register write. */
740 //DDR-VERBOSE = "0";
742 /* Run a short DRAM test after DRAM is initialized as quick check
743 for functionality. This is normally not needed required. Boards
744 with poor DRAM power supplies may use this to detect failures
745 during boot. This should be used in combination with the watchdog
746 timer. */
747 //DDR-TEST-BOOT = "0";
749 /* The DRAM initialization code has the ability to toggle a GPIO to
750 signal when it is running. Boards may need to mux TWSI access
751 between a BMC and the SOC so the BMC can monitor DIMM temperatures
752 and health. This GPIO will be driven high when the SOC may read
753 from the SPDs on the DIMMs. When driven low, another device (BMC)
754 may takeover the TWSI connections to the DIMMS. The default value
755 (-1) disables this feature. */
756 //DDR-CONFIG-GPIO = "-1";
758 /* Scramble DRAM to prevent snooping. This options programs the DRAM
759 controller to scramble addresses and data with random values.
760 Supported values:
761 0: No scrambling
762 1: Always scramble
763 2: Scramble only when using trusted boot (Default) */
764 //DDR-CONFIG-SCRAMBLE = "2";
765 }; /* cavium,bdk */
766 }; /* / */