mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / gigabyte / ga-945gcm-s2l / hda_verb.c
blob654af3a86d922ada90c606fb11514145c70c19c6
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/azalia_device.h>
5 const u32 cim_verb_data[] = {
6 /* coreboot specific header */
7 0x10ec0662, /* Vendor ID */
8 0x1458a002, /* Subsystem ID */
9 10, /* Number of entries */
11 /* Pin Widget Verb Table */
12 AZALIA_PIN_CFG(0, 0x14, 0x01014010),
13 AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)),
14 AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
15 AZALIA_PIN_CFG(0, 0x18, 0x01a19830),
16 AZALIA_PIN_CFG(0, 0x19, 0x02a19c31),
17 AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
18 AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f),
19 AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
20 AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),
21 AZALIA_PIN_CFG(0, 0x1e, 0x014b6120),
24 const u32 pc_beep_verbs[0] = {};
25 AZALIA_ARRAY_SIZES;