mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / google / drallion / Kconfig
blob484fd027cadfef6ac5eb9ca43f94496a5d6b8732
1 ## SPDX-License-Identifier: GPL-2.0-only
3 config BOARD_GOOGLE_BASEBOARD_DRALLION
4         def_bool n
5         select BOARD_ROMSIZE_KB_32768
6         select DRIVERS_GFX_GENERIC
7         select DRIVERS_I2C_GENERIC
8         select DRIVERS_I2C_HID
9         select DRIVERS_INTEL_ISH
10         select DRIVERS_SPI_ACPI
11         select DRIVERS_USB_ACPI
12         select EC_GOOGLE_WILCO
13         select GOOGLE_SMBIOS_MAINBOARD_VERSION
14         select HAVE_ACPI_RESUME
15         select HAVE_ACPI_TABLES
16         select HAVE_SPD_IN_CBFS
17         select I2C_TPM
18         select INTEL_GMA_HAVE_VBT
19         select INTEL_LPSS_UART_FOR_CONSOLE
20         select MAINBOARD_HAS_CHROMEOS
21         select MAINBOARD_HAS_TPM2
22         select MAINBOARD_USES_IFD_EC_REGION
23         select SMBIOS_SERIAL_FROM_VPD if VPD
24         select SOC_INTEL_COMETLAKE_1
25         select SOC_INTEL_COMMON_BLOCK_HDA_VERB
26         select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE
27         select SYSTEM_TYPE_LAPTOP
28         select TPM_GOOGLE_CR50
30 config BOARD_GOOGLE_DRALLION
31         select BOARD_GOOGLE_BASEBOARD_DRALLION
33 if BOARD_GOOGLE_BASEBOARD_DRALLION
35 config DISABLE_HECI1_AT_PRE_BOOT
36         default y
38 config CHROMEOS
39         select GBB_FLAG_FORCE_DEV_SWITCH_ON
40         select GBB_FLAG_FORCE_DEV_BOOT_USB
41         select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
42         select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
44 config CHROMEOS_WIFI_SAR
45         bool "Enable SAR options for ChromeOS build"
46         depends on CHROMEOS
47         select DSAR_ENABLE
48         select GEO_SAR_ENABLE
49         select SAR_ENABLE
50         select USE_SAR
52 config DIMM_MAX
53         default 2
55 config DRIVER_TPM_I2C_BUS
56         hex
57         default 0x4
59 config DRIVER_TPM_I2C_ADDR
60         hex
61         default 0x50
63 config TPM_TIS_ACPI_INTERRUPT
64         int
65         default 82  # GPE0_DW2_18 (GPP_D18)
67 config POWER_OFF_ON_CR50_UPDATE
68         bool
69         default n
71 config MAINBOARD_DIR
72         default "google/drallion"
74 config MAINBOARD_FAMILY
75         string
76         default "Google_Drallion" if BOARD_GOOGLE_DRALLION
78 config MAINBOARD_PART_NUMBER
79         default "Drallion" if BOARD_GOOGLE_DRALLION
81 config UART_FOR_CONSOLE
82         int
83         default 0 if BOARD_GOOGLE_DRALLION
85 config VARIANT_DIR
86         default "drallion" if BOARD_GOOGLE_DRALLION
88 config DEVICETREE
89         default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
91 config VBOOT
92         select HAS_RECOVERY_MRC_CACHE
93         select VBOOT_LID_SWITCH
95 config FMDFILE
96         default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS
98 endif # BOARD_GOOGLE_BASEBOARD_DRALLION