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HEAD
mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git]
/
src
/
mainboard
/
google
/
mistral
/
chromeos.fmd
blob
ccdfbde006bb8f8880de1c0e0eb7d536a87fc7a1
1
## SPDX-License-Identifier: GPL-2.0-only
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FLASH@0x0 8M {
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WP_RO 4M {
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RO_SECTION 0x204000 {
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BOOTBLOCK 128K
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COREBOOT(CBFS)
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FMAP@0x200000 0x1000
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GBB 0x2f00
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RO_FRID 0x100
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}
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RO_VPD(PRESERVE) 128K
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RO_DDR_TRAINING(PRESERVE) 8K
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}
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RW_VPD(PRESERVE) 32K
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RW_NVRAM(PRESERVE) 16K
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RW_DDR_TRAINING(PRESERVE) 8K
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RW_ELOG(PRESERVE) 4K
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RW_SHARED 4K {
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SHARED_DATA
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}
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RW_SECTION_A 1280K {
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VBLOCK_A 8K
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FW_MAIN_A(CBFS)
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RW_FWID_A 256
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}
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RW_SECTION_B 1280K {
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VBLOCK_B 8K
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FW_MAIN_B(CBFS)
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RW_FWID_B 256
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}
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RW_LEGACY(CBFS)
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}