mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3

[coreboot2.git] / src / mainboard / google / rambi / variants / banjo / overridetree.cb

chip soc/intel/baytrail

        register "sdcard_cap_low" = "0x0"

        # Allow PCIe devices to wake system from suspend
        register "pcie_wake_enable" = "1"

        device domain 0 on
                device pci 12.0 off end # SD
        end
end