src/mainboard/google/reef/ec.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <console/console.h>
   5 #include <ec/ec.h>
   6 #include <ec/google/chromeec/ec.h>
   7 #include <intelblocks/lpc_lib.h>
   8 #include <variant/ec.h>
   9
  10 static void ramstage_ec_init(void)
  11 {
  12         const struct google_chromeec_event_info info = {
  13                 .log_events = MAINBOARD_EC_LOG_EVENTS,
  14                 .sci_events = MAINBOARD_EC_SCI_EVENTS,
  15                 .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
  16                 .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
  17                 .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
  18         };
  19
  20         printk(BIOS_INFO, "mainboard: EC init\n");
  21
  22         google_chromeec_events_init(&info, acpi_is_wakeup_s3());
  23 }
  24
  25 static void bootblock_ec_init(void)
  26 {
  27         uint16_t ec_ioport_base;
  28         size_t ec_ioport_size;
  29
  30         /*
  31         * Set up LPC decoding for the ChromeEC I/O port ranges:
  32         * - Ports 62/66, 60/64, and 200->208
  33         * - ChromeEC specific communication I/O ports.
  34         */
  35         lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64
  36                 | LPC_IOE_LGE_200);
  37         google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
  38         lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
  39 }
  40
  41 void mainboard_ec_init(void)
  42 {
  43         if (ENV_RAMSTAGE)
  44                 ramstage_ec_init();
  45         else if (ENV_BOOTBLOCK)
  46                 bootblock_ec_init();
  47 }