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mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / google / reef / variants / snappy / devicetree.cb
blobfd30ce7bae88ea23e5557f7cffe84a113d078ed3
1 chip soc/intel/apollolake
2
3 register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
4 # Disable unused clkreq of PCIe root ports
5 register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
6 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
7 register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
8 register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
9 register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
10
11 # GPIO for PERST_0
12 # If the Board has PERST_0 signal, assign the GPIO
13 # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
14 register "prt0_gpio" = "GPIO_122"
15
16 # GPIO for SD card detect
17 register "sdcard_cd_gpio" = "GPIO_177"
18
19 # EMMC TX DATA Delay 1
20 # Refer to EDS-Vol2-22.3.
21 # [14:8] steps of delay for HS400, each 125ps.
22 # [6:0] steps of delay for SDR104/HS200, each 125ps.
23 register "emmc_tx_data_cntl1" = "0x0C16"
24
25 # EMMC TX DATA Delay 2
26 # Refer to EDS-Vol2-22.3.
27 # [30:24] steps of delay for SDR50, each 125ps.
28 # [22:16] steps of delay for DDR50, each 125ps.
29 # [14:8] steps of delay for SDR25/HS50, each 125ps.
30 # [6:0] steps of delay for SDR12, each 125ps.
31 register "emmc_tx_data_cntl2" = "0x28162828"
32
33 # EMMC RX CMD/DATA Delay 1
34 # Refer to EDS-Vol2-22.3.
35 # [30:24] steps of delay for SDR50, each 125ps.
36 # [22:16] steps of delay for DDR50, each 125ps.
37 # [14:8] steps of delay for SDR25/HS50, each 125ps.
38 # [6:0] steps of delay for SDR12, each 125ps.
39 register "emmc_rx_cmd_data_cntl1" = "0x00181717"
40
41 # EMMC RX CMD/DATA Delay 2
42 # Refer to EDS-Vol2-22.3.
43 # [17:16] stands for Rx Clock before Output Buffer
44 # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
45 # [6:0] steps of delay for HS200, each 125ps.
46 register "emmc_rx_cmd_data_cntl2" = "0x10008"
47
48 # Enable DPTF
49 register "dptf_enable" = "1"
50
51 # PL1 override 12 W: the energy calculation is wrong with the
52 # current VR solution. Experiments show that SoC TDP max (6W) can
53 # be reached when RAPL PL1 is set to 12W.
54 # Set RAPL PL2 to 15W.
55 register "power_limits_config" = "{
56 .tdp_pl1_override = 12,
57 .tdp_pl2_override = 15,
58 }"
59
60 # Enable Audio Clock and Power gating
61 register "hdaudio_clk_gate_enable" = "1"
62 register "hdaudio_pwr_gate_enable" = "1"
63 register "hdaudio_bios_config_lockdown" = "1"
64
65 # Enable lpss s0ix
66 register "lpss_s0ix_enable" = "true"
67
68 # GPE configuration
69 # Note that GPE events called out in ASL code rely on this
70 # route, i.e., if this route changes then the affected GPE
71 # offset bits also need to be changed. This sets the PMC register
72 # GPE_CFG fields.
73 register "gpe0_dw1" = "PMC_GPE_N_31_0"
74 register "gpe0_dw2" = "PMC_GPE_N_63_32"
75 register "gpe0_dw3" = "PMC_GPE_SW_31_0"
76
77 # Intel Common SoC Config
78 #+-------------------+---------------------------+
79 #| Field | Value |
80 #+-------------------+---------------------------+
81 #| I2C0 | Audio |
82 #| I2C2 | TPM |
83 #| I2C3 | Touchscreen |
84 #| I2C4 | Trackpad |
85 #| I2C5 | Digitizer |
86 #+-------------------+---------------------------+
87 register "common_soc_config" = "{
88 .i2c[0] = {
89 .speed = I2C_SPEED_FAST,
90 .rise_time_ns = 44,
91 .fall_time_ns = 22,
92 },
93 .i2c[2] = {
94 .early_init = 1,
95 .speed = I2C_SPEED_FAST,
96 .rise_time_ns = 40,
97 .fall_time_ns = 20,
98 },
99 .i2c[3] = {
100 .speed = I2C_SPEED_FAST,
101 .rise_time_ns = 70,
102 .fall_time_ns = 164,
103 },
104 .i2c[4] = {
105 .speed = I2C_SPEED_FAST,
106 .rise_time_ns = 20,
107 .fall_time_ns = 164,
108 },
109 .i2c[5] = {
110 .speed = I2C_SPEED_FAST,
111 .rise_time_ns = 152,
112 .fall_time_ns = 30,
113 },
114 }"
115
116 # Minimum SLP S3 assertion width 28ms.
117 register "slp_s3_assertion_width_usecs" = "28000"
118
119 # Override USB2 PER PORT register (PORT 1)
120 register "usb2eye[1]" = "{
121 .Usb20PerPortPeTxiSet = 7,
122 .Usb20PerPortTxiSet = 0,
123 }"
124
125 device domain 0 on
126 device pci 00.0 on end # - Host Bridge
127 device pci 00.1 on end # - DPTF
128 device pci 00.2 off end # - NPK
129 device pci 02.0 on # - Gen
130 register "gfx" = "GMA_DEFAULT_PANEL(0)"
131 end
132 device pci 03.0 off end # - Iunit
133 device pci 0d.0 on end # - P2SB
134 device pci 0d.1 on end # - PMC
135 device pci 0d.2 on end # - SPI
136 device pci 0d.3 on end # - Shared SRAM
137 device pci 0e.0 on # - Audio
138 chip drivers/generic/max98357a
139 register "hid" = ""MX98357A""
140 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
141 register "sdmode_delay" = "5"
142 device generic 0 on end
143 end
144 end
145 device pci 0f.0 on end # - CSE
146 device pci 11.0 off end # - ISH
147 device pci 12.0 off end # - SATA
148 device pci 13.0 off end # - Root Port 2 - PCIe-A 0
149 device pci 13.1 off end # - Root Port 3 - PCIe-A 1
150 device pci 13.2 off end # - Root Port 4 - PCIe-A 2
151 device pci 13.3 off end # - Root Port 5 - PCIe-A 3
152 device pci 14.0 on
153 chip drivers/wifi/generic
154 register "wake" = "GPE0_DW3_00"
155 device pci 00.0 on end
156 end
157 end # - Root Port 0 - PCIe-B 0 - Wifi
158 device pci 14.1 off end # - Root Port 1 - PCIe-B 1
159 device pci 15.0 on end # - XHCI
160 device pci 15.1 off end # - XDCI
161 device pci 16.0 on # - I2C 0
162 chip drivers/i2c/da7219
163 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
164 register "btn_cfg" = "50"
165 register "mic_det_thr" = "200"
166 register "jack_ins_deb" = "20"
167 register "jack_det_rate" = ""32ms_64ms""
168 register "jack_rem_deb" = "1"
169 register "a_d_btn_thr" = "0xa"
170 register "d_b_btn_thr" = "0x16"
171 register "b_c_btn_thr" = "0x21"
172 register "c_mic_btn_thr" = "0x3e"
173 register "btn_avg" = "4"
174 register "adc_1bit_rpt" = "1"
175 register "micbias_lvl" = "2600"
176 register "mic_amp_in_sel" = ""diff""
177 device i2c 1a on end
178 end
179 end
180 device pci 16.1 on end # - I2C 1
181 device pci 16.2 on
182 chip drivers/i2c/tpm
183 register "hid" = ""GOOG0005""
184 register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
185 device i2c 50 on end
186 end
187 end # - I2C 2
188 device pci 16.3 on
189 chip drivers/i2c/generic
190 register "hid" = ""ELAN0001""
191 register "desc" = ""ELAN Touchscreen""
192 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
193 register "detect" = "1"
194 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
195 register "reset_delay_ms" = "20"
196 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
197 register "enable_delay_ms" = "1"
198 register "has_power_resource" = "1"
199 device i2c 10 on end
200 end
201 chip drivers/i2c/generic
202 register "hid" = ""MLFS0000""
203 register "desc" = ""Melfas Touchscreen""
204 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
205 register "detect" = "1"
206 # Melfas TS IC doesn't have reset pin design, current FW also not
207 # declare "ce-gpios" in ACPI _DSD to let Melfas TS driver to know
208 # "enable gpio#152 (VTSP) but because of kernel bug & Melfas TS driver
209 # is unable to separate clear power sequence path for certain
210 # TS IC (ex: MIT-410) and kernel will still obstain GPIO from _CRS
211 # by index "0" since no matched "gpio" in ACPI _DSD.
212 # coreboot needs to have "dummy pin" as workaround in order to let
213 # kernel driver grab "useless" GPIO to prevent Melfas TS driver cut
214 # power by driver itself.
215 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
216 register "reset_delay_ms" = "1"
217 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
218 register "enable_delay_ms" = "5"
219 register "has_power_resource" = "1"
220 device i2c 34 on end
221 end
222 chip drivers/i2c/generic
223 register "hid" = ""RAYD0001""
224 register "desc" = ""Raydium Touchscreen""
225 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
226 register "detect" = "1"
227 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
228 register "reset_delay_ms" = "1"
229 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
230 register "enable_delay_ms" = "50"
231 register "has_power_resource" = "1"
232 device i2c 39 on end
233 end
234 chip drivers/i2c/hid
235 register "generic.hid" = ""WDHT0002""
236 register "generic.desc" = ""WDT Touchscreen""
237 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
238 register "generic.detect" = "1"
239 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
240 register "generic.reset_delay_ms" = "130"
241 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
242 register "generic.enable_delay_ms" = "1"
243 register "generic.has_power_resource" = "1"
244 register "hid_desc_reg_offset" = "0x20"
245 device i2c 2c on end
246 end
247 chip drivers/i2c/hid
248 register "generic.hid" = ""GTCH7503""
249 register "generic.desc" = ""G2TOUCH Touchscreen""
250 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
251 register "generic.detect" = "1"
252 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
253 register "generic.reset_delay_ms" = "50"
254 register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
255 register "generic.enable_delay_ms" = "1"
256 register "generic.has_power_resource" = "1"
257 register "hid_desc_reg_offset" = "0x01"
258 device i2c 40 on end
259 end
260 end # - I2C 3
261 device pci 17.0 on
262 chip drivers/i2c/generic
263 register "hid" = ""ELAN0000""
264 register "desc" = ""ELAN Touchpad""
265 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
266 register "wake" = "GPE0_DW1_15"
267 register "detect" = "1"
268 device i2c 15 on end
269 end
270 end # - I2C 4
271 device pci 17.1 on
272 chip drivers/i2c/hid
273 register "generic.hid" = ""WCOM50C1""
274 register "generic.desc" = ""WCOM Digitizer""
275 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
276 register "hid_desc_reg_offset" = "0x1"
277 device i2c 0x9 on end
278 end
279 end # - I2C 5
280 device pci 17.2 off end # - I2C 6
281 device pci 17.3 off end # - I2C 7
282 device pci 18.0 on end # - UART 0
283 device pci 18.1 on end # - UART 1
284 device pci 18.2 on end # - UART 2
285 device pci 18.3 off end # - UART 3
286 device pci 19.0 on end # - SPI 0
287 device pci 19.1 off end # - SPI 1
288 device pci 19.2 off end # - SPI 2
289 device pci 1a.0 on end # - PWM
290 device pci 1b.0 on end # - SDCARD
291 device pci 1c.0 on end # - eMMC
292 device pci 1e.0 off end # - SDIO
293 device pci 1f.0 on # - LPC
294 chip ec/google/chromeec
295 device pnp 0c09.0 on end
296 end
297 end
298 device pci 1f.1 on end # - SMBUS
299 end
300 end
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