mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / google / veyron_rialto / Kconfig
blob916d8a65d94fc2d1eb797ade41551067d4718410
1 ## SPDX-License-Identifier: GPL-2.0-only
3 if BOARD_GOOGLE_VEYRON_RIALTO
5 config BOARD_SPECIFIC_OPTIONS
6         def_bool y
7         select BOARD_ROMSIZE_KB_4096
8         select COMMON_CBFS_SPI_WRAPPER
9         select MAINBOARD_HAS_CHROMEOS
10         select SOC_ROCKCHIP_RK3288
11         select SPI_FLASH
12         select SPI_FLASH_GIGADEVICE
13         select SPI_FLASH_WINBOND
14         select I2C_TPM
15         select MAINBOARD_HAS_TPM1
17 config VBOOT
18         select VBOOT_VBNV_FLASH
20 config MAINBOARD_DIR
21         default "google/veyron_rialto"
23 config MAINBOARD_PART_NUMBER
24         default "Veyron_Rialto"
26 config BOOT_DEVICE_SPI_FLASH_BUS
27         int
28         default 2
30 config DRIVER_TPM_I2C_BUS
31         hex
32         default 0x1
34 config DRIVER_TPM_I2C_ADDR
35         hex
36         default 0x20
38 config CONSOLE_SERIAL_UART_ADDRESS
39         hex
40         depends on DRIVERS_UART
41         default 0xFF690000
43 config PMIC_BUS
44         int
45         default 0
47 endif #  BOARD_GOOGLE_VEYRON_RIALTO