mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / google / veyron_rialto / Makefile.mk
blob6c3b7f4c514a7610f94681add4d5423f5fc7d1ee
1 ## SPDX-License-Identifier: GPL-2.0-only
3 bootblock-y += bootblock.c
4 bootblock-y += boardid.c
5 bootblock-y += chromeos.c
6 bootblock-y += reset.c
8 verstage-y += boardid.c
9 verstage-y += chromeos.c
10 verstage-y += reset.c
12 romstage-y += boardid.c
13 romstage-y += chromeos.c
14 romstage-y += romstage.c
15 romstage-y += sdram_configs.c
16 romstage-y += reset.c
18 ramstage-y += boardid.c
19 ramstage-y += chromeos.c
20 ramstage-y += mainboard.c
21 ramstage-y += reset.c