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mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git]
/
src
/
mainboard
/
google
/
veyron_rialto
/
sdram_inf
/
sdram-lpddr3-K4E8E304EE-1GB.inc
blob
9afd04fdd1ac3e51f14957ca91ddd0f339dfb6c3
1
{
2
{
3
{
4
.rank = 0x2,
5
.col = 0xA,
6
.bk = 0x3,
7
.bw = 0x2,
8
.dbw = 0x2,
9
.row_3_4 = 0x0,
10
.cs0_row = 0xE,
11
.cs1_row = 0xE
12
},
13
{
14
.rank = 0x0,
15
.col = 0x0,
16
.bk = 0x0,
17
.bw = 0x0,
18
.dbw = 0x0,
19
.row_3_4 = 0x0,
20
.cs0_row = 0x0,
21
.cs1_row = 0x0
22
}
23
},
24
{
25
.togcnt1u = 0x215,
26
.tinit = 0xC8,
27
.trsth = 0x0,
28
.togcnt100n = 0x35,
29
.trefi = 0x26,
30
.tmrd = 0x2,
31
.trfc = 0x70,
32
.trp = 0x2000D,
33
.trtw = 0x6,
34
.tal = 0x0,
35
.tcl = 0x8,
36
.tcwl = 0x4,
37
.tras = 0x17,
38
.trc = 0x24,
39
.trcd = 0xD,
40
.trrd = 0x6,
41
.trtp = 0x4,
42
.twr = 0x8,
43
.twtr = 0x4,
44
.texsr = 0x76,
45
.txp = 0x4,
46
.txpdll = 0x0,
47
.tzqcs = 0x30,
48
.tzqcsi = 0x0,
49
.tdqs = 0x1,
50
.tcksre = 0x2,
51
.tcksrx = 0x2,
52
.tcke = 0x4,
53
.tmod = 0x0,
54
.trstl = 0x0,
55
.tzqcl = 0xC0,
56
.tmrr = 0x4,
57
.tckesr = 0x8,
58
.tdpd = 0x1F4
59
},
60
{
61
.dtpr0 = 0x48D7DD93,
62
.dtpr1 = 0x187008D8,
63
.dtpr2 = 0x121076,
64
.mr[0] = 0x0,
65
.mr[1] = 0xC3,
66
.mr[2] = 0x6,
67
.mr[3] = 0x1
68
},
69
.noc_timing = 0x20D266A4,
70
.noc_activate = 0x5B6,
71
.ddrconfig = 2,
72
.ddr_freq = 533*MHz,
73
.dramtype = LPDDR3,
74
.num_channels = 1,
75
.stride = 22,
76
.odt = 0,
77
},