mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / google / zork / smihandler.c
blob298b64760b5ad47ce36de90fb5b7009e09cf476a
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <baseboard/variants.h>
4 #include <console/console.h>
5 #include <cpu/x86/smm.h>
6 #include <ec/google/chromeec/smm.h>
7 #include <gpio.h>
8 #include <soc/smi.h>
9 #include <variant/ec.h>
10 #include <variant/gpio.h>
12 void mainboard_smi_gpi(u32 gpi_sts)
14 printk(BIOS_WARNING, "No GPIO is set up as PAD_SMI, so %s should never end up being "
15 "called. gpi_status is %x.\n", __func__, gpi_sts);
18 void mainboard_smi_sleep(u8 slp_typ)
20 size_t num_gpios;
21 const struct soc_amd_gpio *gpios;
23 if (CONFIG(EC_GOOGLE_CHROMEEC))
24 chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
25 MAINBOARD_EC_S5_WAKE_EVENTS);
27 gpios = variant_sleep_gpio_table(&num_gpios, slp_typ);
28 gpio_configure_pads(gpios, num_gpios);
31 int mainboard_smi_apmc(u8 apmc)
33 if (CONFIG(EC_GOOGLE_CHROMEEC))
34 chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
35 MAINBOARD_EC_SMI_EVENTS);
37 return 0;