src/mainboard/google/zork/variants/baseboard/helpers.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <console/console.h>
   4 #include <inttypes.h>
   5 #include <baseboard/variants.h>
   6 #include <ec/google/chromeec/ec.h>
   7
   8 /* Global definitions for FW_CONFIG values */
   9 enum {
  10         /* Daughterboard index for attributes. */
  11         FW_CONFIG_MASK_DB_INDEX = 0xf,
  12         FW_CONFIG_DB_INDEX_SHIFT = 0,
  13         /* Mainboard USB index for attributes. */
  14         FW_CONFIG_MASK_MB_USB_INDEX = 0xf,
  15         FW_CONFIG_MB_USB_INDEX_SHIFT = 4,
  16         /* Lid accelerometer properties. */
  17         FW_CONFIG_MASK_LID_ACCEL = 0x7,
  18         FW_CONFIG_LID_ACCEL_SHIFT = 8,
  19         /* Base gyro sensor properties. */
  20         FW_CONFIG_MASK_BASE_GYRO = 0x7,
  21         FW_CONFIG_BASE_GYRO_SHIFT = 11,
  22         /* Keyboard backlight presence */
  23         FW_CONFIG_MASK_KEYB_BL = 0x1,
  24         FW_CONFIG_KEYB_BL_SHIFT = 14,
  25         /* Tablet mode supported through lid angle */
  26         FW_CONFIG_MASK_LID_ANGLE_TABLET_MODE = 0x1,
  27         FW_CONFIG_LID_ANGLE_TABLET_MODE_SHIFT = 15,
  28         /* Stylus presence */
  29         FW_CONFIG_MASK_STYLUS = 0x1,
  30         FW_CONFIG_STYLUS_SHIFT = 16,
  31         /* Fingerprint sensor presence */
  32         FW_CONFIG_MASK_FP = 0x1,
  33         FW_CONFIG_SHIFT_FP = 17,
  34         /* NVME presence */
  35         FW_CONFIG_MASK_NVME = 0x1,
  36         FW_CONFIG_SHIFT_NVME = 18,
  37         /* EMMC presence */
  38         FW_CONFIG_MASK_EMMC = 0x1,
  39         FW_CONFIG_SHIFT_EMMC = 19,
  40         /* SD controller type */
  41         FW_CONFIG_MASK_SD_CTRLR = 0x7,
  42         FW_CONFIG_SHIFT_SD_CTRLR = 20,
  43         /* SAR presence */
  44         FW_CONFIG_MASK_SAR = 0x7,
  45         FW_CONFIG_SHIFT_SAR = 23,
  46         /* Mainboard Type for VCORE IC */
  47         FW_CONFIG_MASK_MB_TYPE = 0x1,
  48         FW_CONFIG_SHIFT_MB_TYPE = 26,
  49         /* Fan information */
  50         FW_CONFIG_MASK_FAN = 0x3,
  51         FW_CONFIG_SHIFT_FAN = 27,
  52         /* WWAN presence */
  53         FW_CONFIG_MASK_WWAN = 0x1,
  54         FW_CONFIG_SHIFT_WWAN = 29,
  55         /* Audio AMP type */
  56         FW_CONFIG_MASK_AUDIO_AMP = 0x1,
  57         FW_CONFIG_SHIFT_AUDIO_AMP = 35,
  58         /* Audio codec type */
  59         FW_CONFIG_MASK_AUDIO_CODEC_SOURCE = 0x3,
  60         FW_CONFIG_SHIFT_AUDIO_CODEC_SOURCE = 36,
  61 };
  62
  63 static int get_fw_config(uint64_t *val)
  64 {
  65         static uint64_t known_value;
  66
  67         if (known_value) {
  68                 *val = known_value;
  69                 return 0;
  70         }
  71
  72         if (google_chromeec_cbi_get_fw_config(&known_value) != 0) {
  73                 printk(BIOS_ERR, "FW_CONFIG not set in CBI\n");
  74                 return -1;
  75         }
  76
  77         *val = known_value;
  78
  79         return 0;
  80 }
  81
  82 static unsigned int extract_field(uint64_t mask, int shift)
  83 {
  84         uint64_t fw_config;
  85
  86         /* On errors nothing is assumed to be set. */
  87         if (get_fw_config(&fw_config))
  88                 return 0;
  89
  90         return (fw_config >> shift) & mask;
  91 }
  92
  93 int variant_gets_sar_config(void)
  94 {
  95         return extract_field(FW_CONFIG_MASK_SAR, FW_CONFIG_SHIFT_SAR);
  96 }
  97
  98 int variant_gets_mb_type_config(void)
  99 {
 100         return extract_field(FW_CONFIG_MASK_MB_TYPE, FW_CONFIG_SHIFT_MB_TYPE);
 101 }
 102
 103 int variant_has_emmc(void)
 104 {
 105         return !!extract_field(FW_CONFIG_MASK_EMMC, FW_CONFIG_SHIFT_EMMC);
 106 }
 107
 108 int variant_has_nvme(void)
 109 {
 110         return !!extract_field(FW_CONFIG_MASK_NVME, FW_CONFIG_SHIFT_NVME);
 111 }
 112
 113 int variant_has_wwan(void)
 114 {
 115         return !!extract_field(FW_CONFIG_MASK_WWAN, FW_CONFIG_SHIFT_WWAN);
 116 }
 117
 118 int variant_is_convertible(void)
 119 {
 120         return !!extract_field(FW_CONFIG_MASK_LID_ANGLE_TABLET_MODE,
 121                                FW_CONFIG_LID_ANGLE_TABLET_MODE_SHIFT);
 122 }
 123
 124 bool variant_uses_v3_schematics(void)
 125 {
 126         uint32_t board_version;
 127
 128         if (!CONFIG(VARIANT_SUPPORTS_PRE_V3_SCHEMATICS))
 129                 return true;
 130
 131         if (google_chromeec_cbi_get_board_version(&board_version) != 0)
 132                 return false;
 133
 134         if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)
 135                 return false;
 136
 137         return true;
 138 }
 139
 140 bool variant_uses_v3_6_schematics(void)
 141 {
 142         uint32_t board_version;
 143
 144         if (!CONFIG(VARIANT_SUPPORTS_PRE_V3_6_SCHEMATICS))
 145                 return true;
 146
 147         if (google_chromeec_cbi_get_board_version(&board_version) != 0)
 148                 return false;
 149
 150         if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_V3_6_SCHEMATICS)
 151                 return false;
 152
 153         return true;
 154 }
 155
 156 /*
 157  * pre-v3.6, CODEC_GPI was used as headphone jack interrupt.
 158  * Starting v3.6 this was changed to a separate GPIO.
 159  */
 160 bool variant_uses_codec_gpi(void)
 161 {
 162         return !variant_uses_v3_6_schematics();
 163 }
 164
 165 bool variant_has_active_low_wifi_power(void)
 166 {
 167         uint32_t board_version;
 168
 169         if (!CONFIG(VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH))
 170                 return true;
 171
 172         if (google_chromeec_cbi_get_board_version(&board_version) != 0)
 173                 return false;
 174
 175         if ((int)board_version < CONFIG_VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW)
 176                 return false;
 177
 178         return true;
 179 }
 180
 181 int variant_get_daughterboard_id(void)
 182 {
 183         return extract_field(FW_CONFIG_MASK_DB_INDEX, FW_CONFIG_DB_INDEX_SHIFT);
 184 }
 185
 186 __weak bool variant_has_fingerprint(void)
 187 {
 188         if (CONFIG(VARIANT_HAS_FPMCU))
 189                 return true;
 190
 191         return false;
 192 }
 193
 194 bool fpmcu_needs_delay(void)
 195 {
 196         /*
 197          *  Older board versions need an extra delay here to finish resetting
 198          *  the FPMCU.  The resistor value in the glitch prevention circuit was
 199          *  sized so that the FPMCU doesn't turn of for ~1 second.  On newer
 200          *  boards, that's been updated to ~30ms, which allows the FPMCU's
 201          *  reset to be completed in the time between bootblock and finalize.
 202          */
 203         uint32_t board_version;
 204
 205         if (google_chromeec_cbi_get_board_version(&board_version))
 206                 board_version = 1;
 207
 208         if (board_version <= CONFIG_VARIANT_MAX_BOARD_ID_BROKEN_FMPCU_POWER)
 209                 return true;
 210
 211         return false;
 212 }