src/mainboard/google/zork/variants/vilboz/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <gpio.h>
   6 #include <ec/google/chromeec/ec.h>
   7
   8 static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
   9         /* TP */
  10         PAD_NC(GPIO_32),
  11         /* EN_DEV_BEEP_L */
  12         PAD_GPO(GPIO_89, HIGH),
  13         /* USI_RESET */
  14         PAD_GPO(GPIO_140, HIGH),
  15 };
  16
  17 static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = {
  18         /* P sensor INT */
  19         PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY),
  20         /* LTE_RST_L */
  21         PAD_GPO(GPIO_89, HIGH),
  22 };
  23
  24 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
  25 {
  26         uint32_t board_version;
  27
  28         /*
  29          * If board version cannot be read, assume that this is an older revision of the board
  30          * and so apply overrides. If board version is provided by the EC, then apply overrides
  31          * if version < 2.
  32          */
  33         if (google_chromeec_cbi_get_board_version(&board_version) != 0)
  34                 board_version = 1;
  35
  36         if (board_version < 2) {
  37                 *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram);
  38                 return bid_1_gpio_set_stage_ram;
  39         }
  40
  41         *size = ARRAY_SIZE(vilboz_gpio_set_stage_ram);
  42         return vilboz_gpio_set_stage_ram;
  43 }