mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / hp / snb_ivb_desktops / acpi / pci.asl
blobff3866a25897e9fe735fd3b47a84c8b13b3d717c
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 // Intel PCI to PCI bridge 0:1e.0
5 Device (PCIB)
7         Name (_ADR, 0x001e0000)
8         Name (_PRW, Package() { 13, 4 }) // Power Resources for Wake
10         Method (_PRT)  // _PRT: PCI Interrupt Routing Table
11         {
12                 If (PICM) {
13                         Return (Package() {
14                                 Package() { 0x0000ffff, 0, 0, 0x14 },
15                                 Package() { 0x0000ffff, 1, 0, 0x15 },
16                                 Package() { 0x0000ffff, 2, 0, 0x16 },
17                                 Package() { 0x0000ffff, 3, 0, 0x17 },
18                                 Package() { 0x0001ffff, 0, 0, 0x15 },
19                                 Package() { 0x0001ffff, 1, 0, 0x16 },
20                                 Package() { 0x0001ffff, 2, 0, 0x17 },
21                                 Package() { 0x0001ffff, 3, 0, 0x14 },
22                         })
23                 }
24                 Return (Package() {
25                         Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
26                         Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
27                         Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },
28                         Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
29                         Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
30                         Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
31                         Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
32                         Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
33                 })
34         }