mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3

[coreboot2.git] / src / mainboard / inventec / transformers / devicetree.cb

## SPDX-License-Identifier: GPL-2.0-or-later

chip soc/intel/xeon_sp/spr
        # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
        register "turbo_ratio_limit" = "0x181819191e242424"
        register "turbo_ratio_limit_cores" = "0x3836322e2a1c1a18"

        device domain 0 on
                device pci 16.0 on  end # Management Engine Interface 1
                device pci 16.1 on end # Management Engine Interface 2
                device pci 16.6 on end # Management Engine IDE-R
                device pci 1f.0 on         # Intel device 1b81: PCH eSPI controller
                        chip superio/common
                                device pnp 2e.0 on
                                        chip superio/aspeed/ast2400
                                                register "use_espi" = "1"
                                                device pnp 2e.2 on      # SUART1
                                                        io 0x60 = 0x3f8
                                                        irq 0x70 = 4
                                                end
                                                device pnp 2e.3 on      # SUART2
                                                        io 0x60 = 0x2f8
                                                        irq 0x70 = 3
                                                end
                                                device pnp 2e.4 off      # System Wake-Up Control
                                                end
                                                device pnp 2e.5 off      # Keyboard controller
                                                end
                                                device pnp 2e.7 off      # GPIO
                                                end
                                                device pnp 2e.b off      # Com3
                                                end
                                                device pnp 2e.c off      # Com4
                                                end
                                                device pnp 2e.d off      # LPC 2 AHB
                                                end
                                                device pnp 2e.e off      # Mailbox
                                                end
                                        end
                                end
                        end
                        chip drivers/ipmi # BMC KCS
                                device pnp ca2.0 on end
                                register "bmc_i2c_address" = "0x20"
                                register "bmc_boot_timeout" = "60"
                                register "wait_for_bmc" = "1"
                        end
                        device pnp 0c31.0 off
                        end
                end
        end
end