1 ## SPDX
-License
-Identifier
: GPL
-2.0-only
4 # Enable deep Sx states
5 register
"deep_s5_enable_ac" = "1"
6 register
"deep_s5_enable_dc" = "1"
7 register
"deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
9 register
"eist_enable" = "true"
12 # Note that GPE events called out in ASL code rely on this
13 # route. i.e.
If this route changes
then the affected GPE
14 # offset bits also need
to be changed.
15 register
"gpe0_dw0" = "GPP_G"
16 register
"gpe0_dw1" = "GPP_D"
17 register
"gpe0_dw2" = "GPP_E"
19 # Enabling SLP_S3#
, SLP_S4#
, SLP_SUS
and SLP_A Stretch
20 # SLP_S3 Minimum Assertion Width. Values
0: 60us
, 1: 1ms
, 2: 50ms
, 3: 2s
21 register
"PmConfigSlpS3MinAssert" = "0x02"
23 # SLP_S4 Minimum Assertion Width. Values
0: default
, 1: 1s
, 2: 2s
, 3: 3s
, 4: 4s
24 register
"PmConfigSlpS4MinAssert" = "0x04"
26 # SLP_SUS Minimum Assertion Width. Values
0: 0ms
, 1: 500ms
, 2: 1s
, 3: 4s
27 register
"PmConfigSlpSusMinAssert" = "0x03"
29 # SLP_A Minimum Assertion Width. Values
0: 0ms
, 1: 4s
, 2: 98ms
, 3: 2s
30 register
"PmConfigSlpAMinAssert" = "0x03"
33 register
"power_limits_config" = "{
34 .tdp_pl2_override = 65,
37 register
"SerialIoDevMode" = "{
38 [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
41 # VR Settings Configuration
for 4 Domains
42 #
+----------------+-------+-------+-------+-------+
43 #| Domain
/Setting | SA | IA | GTUS | GTS |
44 #
+----------------+-------+-------+-------+-------+
45 #| Psi1Threshold |
20A |
20A |
20A |
20A |
46 #| Psi2Threshold |
4A |
5A |
5A |
5A |
47 #| Psi3Threshold |
1A |
1A |
1A |
1A |
48 #| Psi3Enable |
1 |
1 |
1 |
1 |
49 #| Psi4Enable |
1 |
1 |
1 |
1 |
50 #| ImonSlope |
0 |
0 |
0 |
0 |
51 #| ImonOffset |
0 |
0 |
0 |
0 |
52 #| IccMax |
11A |
66A |
48A |
48A |
53 #| VrVoltageLimit |
1.52V |
1.52V |
1.52V |
1.52V |
54 #| AcLoadline |
3.9 |
2.1 |
3.1 |
3.1 |
55 #| DcLoadline |
3.9 |
2.1 |
3.1 |
3.1 |
56 #
+----------------+-------+-------+-------+-------+
57 register
"domain_vr_config[VR_SYSTEM_AGENT]" = "{
58 .vr_config_enable = 1,
59 .psi1threshold = VR_CFG_AMP(20),
60 .psi2threshold = VR_CFG_AMP(4),
61 .psi3threshold = VR_CFG_AMP(1),
66 .icc_max = VR_CFG_AMP(11),
67 .voltage_limit = 1520,
72 register
"domain_vr_config[VR_IA_CORE]" = "{
73 .vr_config_enable = 1,
74 .psi1threshold = VR_CFG_AMP(20),
75 .psi2threshold = VR_CFG_AMP(5),
76 .psi3threshold = VR_CFG_AMP(1),
81 .icc_max = VR_CFG_AMP(66),
82 .voltage_limit = 1520,
87 register
"domain_vr_config[VR_GT_UNSLICED]" = "{
88 .vr_config_enable = 1,
89 .psi1threshold = VR_CFG_AMP(20),
90 .psi2threshold = VR_CFG_AMP(5),
91 .psi3threshold = VR_CFG_AMP(1),
96 .icc_max = VR_CFG_AMP(48),
97 .voltage_limit = 1520,
102 register
"domain_vr_config[VR_GT_SLICED]" = "{
103 .vr_config_enable = 1,
104 .psi1threshold = VR_CFG_AMP(20),
105 .psi2threshold = VR_CFG_AMP(5),
106 .psi3threshold = VR_CFG_AMP(1),
111 .icc_max = VR_CFG_AMP(48),
112 .voltage_limit = 1520,
117 # Send an extra VR mailbox command
for the PS4 exit issue
118 register
"SendVrMbxCmd" = "2"
121 subsystemid
0x17aa 0x30d0 inherit
123 register
"PrimaryDisplay" = "Display_iGFX"
125 device ref sa_thermal on
end
126 device ref gmm on
end
127 device ref south_xhci on
128 register
"usb2_ports" = "{
129 [0] = USB2_PORT_MID(OC0), // Front Port 1
130 [1] = USB2_PORT_MID(OC0), // Front Port 2
131 [2] = USB2_PORT_MID(OC1), // Rear Port 3
132 [3] = USB2_PORT_MID(OC2), // Rear Port 4
133 [4] = USB2_PORT_MID(OC3), // Rear Port 5
134 [5] = USB2_PORT_MID(OC4), // Rear Port 6
135 [6] = USB2_PORT_MID(OC1), // Internal header
136 [8] = USB2_PORT_SHORT(OC_SKIP), // M.2 2230
138 register
"usb3_ports" = "{
139 [0] = USB3_PORT_DEFAULT(OC0), // Front Port 1
140 [1] = USB3_PORT_DEFAULT(OC0), // Front Port 2
141 [2] = USB3_PORT_DEFAULT(OC3), // Rear Port 3
142 [3] = USB3_PORT_DEFAULT(OC3), // Rear Port 4
143 [4] = USB3_PORT_DEFAULT(OC1), // Rear Port 5
144 [5] = USB3_PORT_DEFAULT(OC1), // Rear Port 6
147 device ref thermal on
end
148 device ref heci1 on
end
150 register
"SataSalpSupport" = "1"
151 register
"SataPortsEnable" = "{
158 register
"SataPortsHotPlug" = "{
163 device ref pcie_rp17 on # M
.2 2280 / 2242 - SSD
164 register
"PcieRpEnable[16]" = "1"
165 register
"PcieRpClkReqSupport[16]" = "1"
166 register
"PcieRpClkReqNumber[16]" = "1"
167 register
"PcieRpAdvancedErrorReporting[16]" = "1"
168 register
"PcieRpLtrEnable[16]" = "1"
169 register
"PcieRpClkSrcNumber[16]" = "7"
170 register
"PcieRpHotPlug[16]" = "1"
172 device ref pcie_rp7 on # M
.2 2230 - WLAN
173 register
"PcieRpEnable[6]" = "1"
174 register
"PcieRpClkReqSupport[6]" = "1"
175 register
"PcieRpClkReqNumber[6]" = "11"
176 register
"PcieRpAdvancedErrorReporting[6]" = "1"
177 register
"PcieRpLtrEnable[6]" = "1"
178 register
"PcieRpClkSrcNumber[6]" = "1"
179 register
"PcieRpHotPlug[6]" = "1"
180 chip drivers
/wifi
/generic
181 register
"wake" = "GPE0_PCI_EXP"
182 device generic
0 on
end
185 device ref lpc_espi on
186 #
Set LPC Serial IRQ mode
187 register
"serirq_mode" = "SERIRQ_CONTINUOUS"
188 chip superio
/nuvoton
/nct6687d
189 device pnp
2e
.1 off
end # Parallel port
190 device pnp
2e
.2 on # COM1
- optional module
194 device pnp
2e
.3 off
end # COM2
, IR
195 device pnp
2e
.5 off
end # Keyboard
196 device pnp
2e
.6 off
end # CIR
197 device pnp
2e
.7 off
end # GPIO0
-7
198 device pnp
2e
.8 off
end # P80 UART
199 device pnp
2e
.9 off
end # GPIO8
-9, GPIO1
-8 AF
200 device pnp
2e.a on # ACPI
203 device pnp
2e.b on # EC
206 device pnp
2e.c off
end # RTC
207 device pnp
2e.d off
end # Deep Sleep
208 device pnp
2e.e on # TACH
/PWM assignment
212 device pnp
2e.f off
end #
Function register
214 chip drivers
/pc80
/tpm
215 device pnp
0c31.0 on
end
218 device ref hda on
end
219 device ref smbus on
end
220 device ref gbe on
end