mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / lenovo / m920q / Kconfig
bloba83b477a545194fb1a2e2d361f4731a3975065d3
1 # SPDX-License-Identifier: GPL-2.0-only
3 if BOARD_LENOVO_M920Q
5 config BOARD_SPECIFIC_OPTIONS
6         def_bool y
7         select BOARD_ROMSIZE_KB_24576
8         select DRIVERS_UART_8250IO
9         select HAVE_ACPI_RESUME
10         select HAVE_ACPI_TABLES
11         select HAVE_CMOS_DEFAULT
12         select HAVE_OPTION_TABLE
13         select INTEL_GMA_HAVE_VBT
14         select MAINBOARD_HAS_LIBGFXINIT
15         select MAINBOARD_HAS_TPM2
16         select MAINBOARD_USES_IFD_GBE_REGION
17         select MEMORY_MAPPED_TPM
18         select SOC_INTEL_CANNONLAKE_PCH_H
19         select SOC_INTEL_COFFEELAKE
20         select SOC_INTEL_COMMON_BLOCK_HDA_VERB
21         select SUPERIO_NUVOTON_NCT6687D
23 config MAINBOARD_DIR
24         default "lenovo/m920q"
26 config MAINBOARD_PART_NUMBER
27         default "ThinkCentre M920 Tiny"
29 config CBFS_SIZE
30         default 0x900000
32 endif