src/mainboard/pcengines/apu2/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0-only
   2
   3 if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \
   4         BOARD_PCENGINES_APU5
   5
   6 config BOARD_SPECIFIC_OPTIONS
   7         def_bool y
   8         select CPU_AMD_PI_00730F01
   9         select NORTHBRIDGE_AMD_PI_00730F01
  10         select SOUTHBRIDGE_AMD_PI_AVALON
  11         select DEFAULT_POST_ON_LPC
  12         select SUPERIO_NUVOTON_NCT5104D
  13         select HAVE_PIRQ_TABLE
  14         select HAVE_ACPI_TABLES
  15         select HUDSON_FADT_LEGACY_DEVICES
  16         select BOARD_ROMSIZE_KB_8192
  17         select HAVE_SPD_IN_CBFS
  18         select MEMORY_MAPPED_TPM
  19         select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
  20         select PCIEXP_ASPM
  21         select PCIEXP_CLK_PM
  22         select PCIEXP_COMMON_CLOCK
  23         select PCIEXP_L1_SUB_STATE
  24
  25 config MAINBOARD_DIR
  26         default "pcengines/apu2"
  27
  28 config VARIANT_DIR
  29         default "apu2" if BOARD_PCENGINES_APU2
  30         default "apu3" if BOARD_PCENGINES_APU3
  31         default "apu4" if BOARD_PCENGINES_APU4
  32         default "apu5" if BOARD_PCENGINES_APU5
  33
  34 config DEVICETREE
  35         default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
  36
  37 config MAINBOARD_PART_NUMBER
  38         default "apu2" if BOARD_PCENGINES_APU2
  39         default "apu3" if BOARD_PCENGINES_APU3
  40         default "apu4" if BOARD_PCENGINES_APU4
  41         default "apu5" if BOARD_PCENGINES_APU5
  42
  43 config MAX_CPUS
  44         int
  45         default 4
  46
  47 config IRQ_SLOT_COUNT
  48         int
  49         default 11
  50
  51 config ONBOARD_VGA_IS_PRIMARY
  52         bool
  53         default y
  54
  55 config AGESA_BINARY_PI_FILE
  56         string
  57         default "3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
  58
  59 choice
  60         prompt "J19 pins 1-10"
  61         default APU2_PINMUX_UART_C
  62
  63 config APU2_PINMUX_OFF_C
  64         bool "disable"
  65
  66 config APU2_PINMUX_GPIO0
  67         bool "GPIO"
  68         depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \
  69                 BOARD_PCENGINES_APU4
  70
  71 config APU2_PINMUX_UART_C
  72         bool "UART 0x3e8"
  73
  74 endchoice
  75
  76 choice
  77         prompt "J19 pins 11-20"
  78         default APU2_PINMUX_UART_D
  79
  80 config APU2_PINMUX_OFF_D
  81         bool "disable"
  82
  83 config APU2_PINMUX_GPIO1
  84         bool "GPIO"
  85         depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \
  86                 BOARD_PCENGINES_APU4
  87
  88 config APU2_PINMUX_UART_D
  89         bool "UART 0x2e8"
  90
  91 endchoice
  92
  93 config DIMM_SPD_SIZE
  94         default 128
  95
  96 config AGESA_USE_1_0_0_4_HEADER
  97         bool
  98         default y
  99         help
 100           Due to a bug in AGESA 1.0.0.A affecting boards without UMA, it is
 101           impossible to use the newest blob. Using an older 1.0.0.4 blob
 102           workarounds the problem, however some headers changes between blob
 103           revisions. This option removes the changes in headers introduced
 104           with AGESA 1.0.0.A to fit the 1.0.0.4 revision.
 105
 106 endif # BOARD_PCENGINES_APU2