mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / pcengines / apu2 / bootblock.c
blob3fa35af0ad88b65b02e04843908321ec86ad4ac4
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <bootblock_common.h>
4 #include <device/pnp_type.h>
5 #include <southbridge/amd/pi/hudson/hudson.h>
6 #include <superio/nuvoton/common/nuvoton.h>
7 #include <superio/nuvoton/nct5104d/nct5104d.h>
9 #define SIO_PORT 0x2e
10 #define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
11 #define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2)
13 void bootblock_mainboard_early_init(void)
15 hudson_lpc_port80();
16 hudson_clk_output_48Mhz();
18 /* COM2 on apu5 is reserved so only COM1 should be supported */
19 if ((CONFIG_UART_FOR_CONSOLE == 1) &&
20 !CONFIG(BOARD_PCENGINES_APU5))
21 nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
22 else if (CONFIG_UART_FOR_CONSOLE == 0)
23 nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);