src/mainboard/protectli/vault_adl_p/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/cpu.h>
   4 #include <console/console.h>
   5 #include <cpu/x86/name.h>
   6 #include <delay.h>
   7 #include <device/device.h>
   8 #include <intelblocks/systemagent.h>
   9 #include <smbios.h>
  10 #include <soc/ramstage.h>
  11 #include <soc/pcr_ids.h>
  12 #include <soc/tcss.h>
  13 #include <string.h>
  14
  15 #include "board_beep.h"
  16
  17 const char *smbios_mainboard_product_name(void)
  18 {
  19         char processor_name[49];
  20
  21         fill_processor_name(processor_name);
  22
  23         if (strstr(processor_name, "i3-1215U") != NULL)
  24                 return "VP6630";
  25         else if (strstr(processor_name, "i5-1235U") != NULL)
  26                 return "VP6650";
  27         else if (strstr(processor_name, "i7-1255U") != NULL)
  28                 return "VP6670";
  29         else
  30                 return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME;
  31 }
  32
  33 void mainboard_silicon_init_params(FSP_S_CONFIG *params)
  34 {
  35         int i;
  36
  37         memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm));
  38         memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
  39
  40         memset(params->CpuPcieRpEnableCpm, 0, sizeof(params->CpuPcieRpEnableCpm));
  41         memset(params->CpuPcieClockGating, 0, sizeof(params->CpuPcieClockGating));
  42         memset(params->CpuPciePowerGating, 0, sizeof(params->CpuPciePowerGating));
  43         memset(params->CpuPcieRpPmSci, 0, sizeof(params->CpuPcieRpPmSci));
  44
  45         /* Max payload 256B */
  46         memset(params->PcieRpMaxPayload, 1, sizeof(params->PcieRpMaxPayload));
  47
  48         /* CLKREQs connected only to RP5 and RP6 */
  49         params->PcieRpEnableCpm[4] = 1;
  50         params->PcieRpEnableCpm[5] = 1;
  51
  52         /* Type-C PD */
  53         params->PmcPdEnable = 1;
  54         params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; /* GPP_H6 */
  55         params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; /* GPP_H7 */
  56         params->PortResetMessageEnable[7] = 1;
  57
  58         /* IOM USB config */
  59         params->PchUsbOverCurrentEnable = 0;
  60
  61         params->EnableTcssCovTypeA[0] = 1;
  62         params->EnableTcssCovTypeA[1] = 1;
  63         params->EnableTcssCovTypeA[3] = 1;
  64
  65         params->MappingPchXhciUsbA[0] = 1;
  66         params->MappingPchXhciUsbA[1] = 2;
  67         params->MappingPchXhciUsbA[3] = 4;
  68
  69         params->CnviRfResetPinMux = 0;
  70         params->CnviClkreqPinMux = 0;
  71
  72         /*
  73          * Workaround: poll for IOM ready before SiliconInit for 2 seconds. ME
  74          * seems to be too sluggish with its firmware initialization and IOM
  75          * is not ready during TCSS Init in SiliconInit, when serial console
  76          * debugging is disabled in coreboot. Entering FSP SiliconInit without
  77          * IOM ready, will cause the XHCI controller in the CPU to be disabled
  78          * and all USB 3.x ports on the platform non-functional.
  79          */
  80         for (i = 0; i < 200; i++) {
  81                 if (REGBAR32(PID_IOM, IOM_TYPEC_STATUS_1) & IOM_READY)
  82                         return;
  83
  84                 mdelay(10);
  85         }
  86
  87         printk(BIOS_ERR, "TCSS IOM not ready, USB3.0 ports will not be functional\n");
  88 }
  89
  90 static void mainboard_final(void *chip_info)
  91 {
  92         if (CONFIG(BEEP_ON_BOOT))
  93                 do_beep(1500, 100);
  94 }
  95
  96 struct chip_operations mainboard_ops = {
  97         .final = mainboard_final,
  98 };