src/mainboard/supermicro/x9sae/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <device/pnp_ops.h>
   5 #include <southbridge/intel/bd82x6x/pch.h>
   6 #include <superio/nuvoton/common/nuvoton.h>
   7 #include <superio/nuvoton/nct6776/nct6776.h>
   8
   9 #define GLOBAL_DEV PNP_DEV(0x2e, 0)
  10 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
  11 #define ACPI_DEV   PNP_DEV(0x2e, NCT6776_ACPI)
  12
  13 const struct southbridge_usb_port mainboard_usb_ports[] = {
  14         { 1, 0, 0 },
  15         { 1, 0, 0 },
  16         { 1, 0, 1 },
  17         { 1, 0, 1 },
  18         { 1, 0, 2 },
  19         { 1, 0, 2 },
  20         { 1, 0, 3 },
  21         { 1, 0, 3 },
  22         { 1, 0, 4 },
  23         { 1, 0, 4 },
  24         { 1, 0, 6 },
  25         { 1, 0, 5 },
  26         { 1, 0, 5 },
  27         { 1, 0, 6 },
  28 };
  29
  30 void bootblock_mainboard_early_init(void)
  31 {
  32         nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
  33
  34         /* Select SIO pin states */
  35         pnp_write_config(GLOBAL_DEV, 0x1a, 0xc8);
  36         pnp_write_config(GLOBAL_DEV, 0x1b, 0x6d);
  37         pnp_write_config(GLOBAL_DEV, 0x1c, 0x83);
  38         pnp_write_config(GLOBAL_DEV, 0x24, 0x24);
  39         pnp_write_config(GLOBAL_DEV, 0x2a, 0x00);
  40         pnp_write_config(GLOBAL_DEV, 0x2b, 0x02);
  41         pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);
  42
  43         /* Power RAM in S3 */
  44         pnp_set_logical_device(ACPI_DEV);
  45         pnp_write_config(ACPI_DEV, 0xe4, 0x10);
  46
  47         pnp_set_logical_device(SERIAL_DEV);
  48
  49         nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
  50
  51         /* Enable UART */
  52         nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  53 }