mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / mainboard / supermicro / x9sae / hda_verb.c
blob255ecf9a8537b34f21b257f8dd23ba8849ba2bc5
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/azalia_device.h>
5 const u32 cim_verb_data[] = {
6 0x10ec0889, /* Codec Vendor / Device ID: Realtek */
7 0x15d90644, /* Subsystem ID */
8 15, /* Number of 4 dword sets */
9 AZALIA_SUBVENDOR(0, 0x15d90644),
10 AZALIA_PIN_CFG(0, 0x11, 0x18561120),
11 AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
12 AZALIA_PIN_CFG(0, 0x14, 0x01014010),
13 AZALIA_PIN_CFG(0, 0x15, 0x01011012),
14 AZALIA_PIN_CFG(0, 0x16, 0x01016011),
15 AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
16 AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
17 AZALIA_PIN_CFG(0, 0x19, 0x02a19841),
18 AZALIA_PIN_CFG(0, 0x1a, 0x0181344f),
19 AZALIA_PIN_CFG(0, 0x1b, 0x0221401f),
20 AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)),
21 AZALIA_PIN_CFG(0, 0x1d, 0x4007e619),
22 AZALIA_PIN_CFG(0, 0x1e, 0x01452130),
23 AZALIA_PIN_CFG(0, 0x1f, 0x01c41150),
25 0x80862806, /* Codec Vendor / Device ID: Intel */
26 0x80860101, /* Subsystem ID */
27 4, /* Number of 4 dword sets */
28 AZALIA_SUBVENDOR(3, 0x80860101),
29 AZALIA_PIN_CFG(3, 0x05, 0x58560010),
30 AZALIA_PIN_CFG(3, 0x06, 0x18560020),
31 AZALIA_PIN_CFG(3, 0x07, 0x18560030),
35 const u32 pc_beep_verbs[0] = {};
37 AZALIA_ARRAY_SIZES;