src/northbridge/intel/sandybridge/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/mmio.h>
   5 #include <device/device.h>
   6 #include <device/pci_ops.h>
   7 #include <device/pci_def.h>
   8 #include <option.h>
   9 #include <types.h>
  10
  11 #include "sandybridge.h"
  12
  13 static void systemagent_vtd_init(void)
  14 {
  15         const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
  16         if (capid0_a & (1 << 23))
  17                 return;
  18
  19         /* Setup BARs */
  20         mchbar_write32(GFXVTBAR + 4, GFXVT_BASE >> 32);
  21         mchbar_write32(GFXVTBAR + 0, GFXVT_BASE | 1);
  22         mchbar_write32(VTVC0BAR + 4, VTVC0_BASE >> 32);
  23         mchbar_write32(VTVC0BAR + 0, VTVC0_BASE | 1);
  24
  25         /* Lock policies */
  26         write32p(GFXVT_BASE + 0xff0, 0x80000000);
  27
  28         const struct device *const azalia = pcidev_on_root(0x1b, 0);
  29         if (azalia && azalia->enabled) {
  30                 write32p(VTVC0_BASE + 0xff0, 0x20000000);
  31                 write32p(VTVC0_BASE + 0xff0, 0xa0000000);
  32         } else {
  33                 write32p(VTVC0_BASE + 0xff0, 0x80000000);
  34         }
  35 }
  36
  37 static void enable_pam_region(void)
  38 {
  39         pci_write_config8(HOST_BRIDGE, PAM0, 0x30);
  40         pci_write_config8(HOST_BRIDGE, PAM1, 0x33);
  41         pci_write_config8(HOST_BRIDGE, PAM2, 0x33);
  42         pci_write_config8(HOST_BRIDGE, PAM3, 0x33);
  43         pci_write_config8(HOST_BRIDGE, PAM4, 0x33);
  44         pci_write_config8(HOST_BRIDGE, PAM5, 0x33);
  45         pci_write_config8(HOST_BRIDGE, PAM6, 0x33);
  46 }
  47
  48 static void sandybridge_setup_bars(void)
  49 {
  50         printk(BIOS_DEBUG, "Setting up static northbridge registers...");
  51         /* Set up all hardcoded northbridge BARs */
  52         pci_write_config32(HOST_BRIDGE, EPBAR,  CONFIG_FIXED_EPBAR_MMIO_BASE  | 1);
  53         pci_write_config32(HOST_BRIDGE, EPBAR  + 4, 0);
  54         pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
  55         pci_write_config32(HOST_BRIDGE, MCHBAR + 4, 0);
  56         pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
  57         pci_write_config32(HOST_BRIDGE, DMIBAR + 4, 0);
  58
  59         printk(BIOS_DEBUG, " done\n");
  60 }
  61
  62 static void sandybridge_setup_graphics(void)
  63 {
  64         u16 reg16;
  65         u8 gfxsize;
  66
  67         reg16 = pci_read_config16(PCI_DEV(0, 2, 0), PCI_DEVICE_ID);
  68         switch (reg16) {
  69         case 0x0102: /* GT1 Desktop */
  70         case 0x0106: /* GT1 Mobile */
  71         case 0x010a: /* GT1 Server */
  72         case 0x0112: /* GT2 Desktop */
  73         case 0x0116: /* GT2 Mobile */
  74         case 0x0122: /* GT2 Desktop >=1.3GHz */
  75         case 0x0126: /* GT2 Mobile >=1.3GHz */
  76         case 0x0152: /* IvyBridge */
  77         case 0x0156: /* IvyBridge */
  78         case 0x0162: /* IvyBridge */
  79         case 0x0166: /* IvyBridge */
  80         case 0x016a: /* IvyBridge */
  81                 break;
  82         default:
  83                 printk(BIOS_DEBUG, "Graphics not supported by this CPU/chipset.\n");
  84                 return;
  85         }
  86
  87         printk(BIOS_DEBUG, "Initializing Graphics...\n");
  88
  89         /* Fall back to CONFIG_IGD_DEFAULT_UMA_INDEX for IGD memory */
  90         gfxsize = get_uint_option("gfx_uma_size", CONFIG_IGD_DEFAULT_UMA_INDEX);
  91
  92         /* Program IGD memory allocation by setting GGC[7:3] */
  93         reg16 = pci_read_config16(HOST_BRIDGE, GGC);
  94         reg16 &= ~0x00f8;
  95         reg16 |= (gfxsize + 1) << 3;
  96         /* Program GTT memory by setting GGC[9:8] = 2MB */
  97         reg16 &= ~0x0300;
  98         reg16 |= 2 << 8;
  99         /* Enable VGA decode */
 100         reg16 &= ~0x0002;
 101         pci_write_config16(HOST_BRIDGE, GGC, reg16);
 102
 103         /* Enable 256MB aperture */
 104         pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02);
 105
 106         /* Erratum workarounds */
 107         mchbar_setbits32(SAPMCTL, 1 << 9 | 1 << 10);
 108
 109         /* Enable SA Clock Gating */
 110         mchbar_setbits32(SAPMCTL, 1 << 0);
 111
 112         /* GPU RC6 workaround for sighting 366252 */
 113         mchbar_setbits32(SSKPD_HI, 1 << 31);
 114
 115         /* VLW (Virtual Legacy Wire?) */
 116         mchbar_clrbits32(0x6120, 1 << 0);
 117
 118         mchbar_setbits32(INTRDIRCTL, 1 << 4 | 1 << 5);
 119 }
 120
 121 static void start_peg_link_training(void)
 122 {
 123         u32 deven;
 124
 125         const u16 base_rev = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID) & BASE_REV_MASK;
 126         /*
 127          * PEG on IvyBridge+ needs a special startup sequence.
 128          * As the MRC has its own initialization code skip it.
 129          */
 130         if ((base_rev != BASE_REV_IVB) || CONFIG(HAVE_MRC))
 131                 return;
 132
 133         deven = pci_read_config32(HOST_BRIDGE, DEVEN);
 134
 135         /*
 136          * For each PEG device, set bit 5 to use three retries for OC (Offset Calibration).
 137          * We also clear DEFER_OC (bit 16) in order to start PEG training.
 138          */
 139         if (deven & DEVEN_PEG10)
 140                 pci_update_config32(PCI_DEV(0, 1, 0), AFE_PWRON, ~(1 << 16), 1 << 5);
 141
 142         if (deven & DEVEN_PEG11)
 143                 pci_update_config32(PCI_DEV(0, 1, 1), AFE_PWRON, ~(1 << 16), 1 << 5);
 144
 145         if (deven & DEVEN_PEG12)
 146                 pci_update_config32(PCI_DEV(0, 1, 2), AFE_PWRON, ~(1 << 16), 1 << 5);
 147
 148         if (deven & DEVEN_PEG60)
 149                 pci_update_config32(PCI_DEV(0, 6, 0), AFE_PWRON, ~(1 << 16), 1 << 5);
 150 }
 151
 152 void systemagent_early_init(void)
 153 {
 154         const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE;
 155         u32 capid0_a;
 156         u8 reg8;
 157
 158         /* Device ID Override Enable should be done very early */
 159         capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
 160         if (capid0_a & (1 << 10)) {
 161                 reg8 = pci_read_config8(HOST_BRIDGE, DIDOR);
 162                 reg8 &= ~7; /* Clear 2:0 */
 163
 164                 if (is_mobile)
 165                         reg8 |= 1; /* Set bit 0 */
 166
 167                 pci_write_config8(HOST_BRIDGE, DIDOR, reg8);
 168         }
 169
 170         /* Print platform type */
 171         printk(BIOS_INFO, "Detected system type: %s\n", is_mobile ? "mobile" : "desktop");
 172
 173         /* Setup all BARs required for early PCIe and raminit */
 174         sandybridge_setup_bars();
 175
 176         /* Set C0000-FFFFF to access RAM on both reads and writes */
 177         enable_pam_region();
 178
 179         /* Setup IOMMU BARs */
 180         systemagent_vtd_init();
 181
 182         /* Device Enable, don't touch PEG bits */
 183         pci_or_config32(HOST_BRIDGE, DEVEN, DEVEN_IGD);
 184
 185         sandybridge_setup_graphics();
 186
 187         /*
 188          * Write magic values to start PEG link training. This should be done in PCI device
 189          * enumeration, but the PCIe specification requires to wait at least 100msec after
 190          * reset for devices to come up. As we don't want to increase boot time, enable it
 191          * early and assume that PEG is up as soon as PCI enumeration starts.
 192          *
 193          * TODO: use timestamps to ensure the timings are met.
 194          */
 195         start_peg_link_training();
 196 }
 197
 198 void northbridge_romstage_finalize(void)
 199 {
 200         mchbar_write16(SSKPD_HI, 0xcafe);
 201 }