mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / southbridge / intel / i82801dx / bootblock.c
blobcbc12dd95b1de3d73c6099a656fe717fb02c76cb
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <arch/bootblock.h>
4 #include <device/pci_ops.h>
6 #include "i82801dx.h"
8 void bootblock_early_southbridge_init(void)
10 /* Set FWH IDs for 2 MB flash part. */
11 if (CONFIG_ROM_SIZE == 0x200000)
12 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111);
15 /* Setup decode ports and LPC I/F enables. */
16 i82801dx_early_init();
17 i82801dx_lpc_setup();