mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / southbridge / intel / i82801gx / Makefile.mk
blobb6fd0c324a4da2c7c1308d3655621d5f28059906
1 ## SPDX-License-Identifier: GPL-2.0-only
3 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
5 bootblock-y += early_init.c
6 bootblock-y += bootblock.c
8 ramstage-y += i82801gx.c
9 ramstage-y += fadt.c
10 ramstage-y += ac97.c
11 ramstage-y += azalia.c
12 ramstage-y += ide.c
13 ramstage-y += lpc.c
14 ramstage-y += pci.c
15 ramstage-y += pcie.c
16 ramstage-y += sata.c
17 ramstage-y += smbus.c
18 ramstage-y += usb.c
19 ramstage-y += usb_ehci.c
21 smm-y += smihandler.c
23 romstage-y += early_init.c
24 romstage-y += early_cir.c
26 CPPFLAGS_common += -I$(src)/southbridge/intel/i82801gx/include
28 endif