mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / southbridge / intel / i82801gx / ac97.c
blobaa73ae21d4732468c8d2d88f4db88d5694b83116
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <arch/io.h>
8 #include <device/pci_ops.h>
9 #include <delay.h>
10 #include "i82801gx.h"
12 #define NAMBAR 0x10
13 #define MASTER_VOL 0x02
14 #define PAGING 0x24
15 #define EXT_AUDIO 0x28
16 #define FUNC_SEL 0x66
17 #define INFO_IO 0x68
18 #define CONNECTOR 0x6a
19 #define VENDOR_ID1 0x7c
20 #define VENDOR_ID2 0x7e
21 #define SEC_VENDOR_ID1 0xfc
22 #define SEC_VENDOR_ID2 0xfe
24 #define NABMBAR 0x14
25 #define GLOB_CNT 0x2c
26 #define GLOB_STA 0x30
27 #define CAS 0x34
29 #define MMBAR 0x10
30 #define EXT_MODEM_ID1 0x3c
31 #define EXT_MODEM_ID2 0xbc
33 #define MBAR 0x14
34 #define SEC_CODEC 0x40
36 /* FIXME. This table is probably mainboard specific */
37 static u16 ac97_function[16*2][4] = {
38 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
39 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
40 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
41 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
42 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
43 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
44 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
45 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
46 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
47 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
48 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
49 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
50 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
51 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
52 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
53 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
54 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
55 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
56 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
57 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
58 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
59 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
60 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
61 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
62 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
63 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
64 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
65 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
66 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
67 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
68 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
69 { (1 << 5), (2 << 11), (1 << 10), (3 << 13) }
72 static u16 nabmbar;
73 static u16 nambar;
75 static int ac97_semaphore(void)
77 int timeout;
78 u8 reg8;
80 timeout = 0xffff;
81 do {
82 reg8 = inb(nabmbar + CAS);
83 timeout--;
84 } while ((reg8 & 1) && timeout);
85 if (!timeout)
86 printk(BIOS_DEBUG, "Timeout!\n");
88 return (!timeout);
91 static void init_cnr(void)
93 // TODO
96 static void program_sigid(struct device *dev, u32 id)
98 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, id);
101 static void ac97_audio_init(struct device *dev)
103 u16 reg16;
104 u32 reg32;
105 int i;
107 printk(BIOS_DEBUG, "Initializing AC'97 Audio.\n");
109 /* top 16 bits are zero, so don't read them */
110 nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe;
111 nambar = pci_read_config16(dev, NAMBAR) & 0xfffe;
113 reg16 = inw(nabmbar + GLOB_CNT);
114 reg16 |= (1 << 1); /* Remove AC_RESET# */
115 outw(reg16, nabmbar + GLOB_CNT);
117 /* Wait 600ms. Ouch. */
118 udelay(600 * 1000);
120 init_cnr();
122 /* Detect Primary AC'97 Codec */
123 reg32 = inl(nabmbar + GLOB_STA);
124 if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) {
125 /* Primary Codec not found */
126 printk(BIOS_DEBUG, "No primary codec. Disabling AC'97 Audio.\n");
127 return;
130 ac97_semaphore();
132 /* Detect if codec is programmable */
133 outw(0x8000, nambar + MASTER_VOL);
134 ac97_semaphore();
135 if (inw(nambar + MASTER_VOL) != 0x8000) {
136 printk(BIOS_DEBUG, "Codec not programmable. Disabling AC'97 Audio.\n");
137 return;
140 /* Program Vendor IDs */
141 reg32 = inw(nambar + VENDOR_ID1);
142 reg32 <<= 16;
143 reg32 |= (u16)inw(nambar + VENDOR_ID2);
145 program_sigid(dev, reg32);
147 /* Is Codec AC'97 2.3 compliant? */
148 reg16 = inw(nambar + EXT_AUDIO);
149 /* [11:10] = 10b -> AC'97 2.3 */
150 if ((reg16 & 0x0c00) != 0x0800) {
151 /* No 2.3 Codec. We're done */
152 return;
155 /* Select Page 1 */
156 reg16 = inw(nambar + PAGING);
157 reg16 &= 0xfff0;
158 reg16 |= 0x0001;
159 outw(reg16, nambar + PAGING);
161 for (i = 0x0a * 2; i > 0; i--) {
162 outw(i, nambar + FUNC_SEL);
164 /* Function could not be selected. Next one */
165 if (inw(nambar + FUNC_SEL) != i)
166 continue;
168 reg16 = inw(nambar + INFO_IO);
170 /* Function Information present? */
171 if (!(reg16 & (1 << 0)))
172 continue;
174 /* Function Information valid? */
175 if (!(reg16 & (1 << 4)))
176 continue;
178 /* Program Buffer Delay [9:5] */
179 reg16 &= 0x03e0;
180 reg16 |= ac97_function[i][0];
182 /* Program Gain [15:11] */
183 reg16 |= ac97_function[i][1];
185 /* Program Inversion [10] */
186 reg16 |= ac97_function[i][2];
188 outw(reg16, nambar + INFO_IO);
190 /* Program Connector / Jack Location */
191 reg16 = inw(nambar + CONNECTOR);
192 reg16 &= 0x1fff;
193 reg16 |= ac97_function[i][3];
194 outw(reg16, nambar + CONNECTOR);
198 static void ac97_modem_init(struct device *dev)
200 u16 reg16;
201 u32 reg32;
202 u16 mmbar, mbar;
204 mmbar = pci_read_config16(dev, MMBAR) & 0xfffe;
205 mbar = pci_read_config16(dev, MBAR) & 0xfffe;
207 reg16 = inw(mmbar + EXT_MODEM_ID1);
208 if ((reg16 & 0xc000) != 0xc000) {
209 if (reg16 & (1 << 0)) {
210 reg32 = inw(mmbar + VENDOR_ID2);
211 reg32 <<= 16;
212 reg32 |= (u16)inw(mmbar + VENDOR_ID1);
213 program_sigid(dev, reg32);
214 return;
218 /* Secondary codec? */
219 reg16 = inw(mbar + SEC_CODEC);
220 if ((reg16 & (1 << 9)) == 0)
221 return;
223 reg16 = inw(mmbar + EXT_MODEM_ID2);
224 if ((reg16 & 0xc000) == 0x4000) {
225 if (reg16 & (1 << 0)) {
226 reg32 = inw(mmbar + SEC_VENDOR_ID2);
227 reg32 <<= 16;
228 reg32 |= (u16)inw(mmbar + SEC_VENDOR_ID1);
229 program_sigid(dev, reg32);
230 return;
235 static struct device_operations ac97_audio_ops = {
236 .read_resources = pci_dev_read_resources,
237 .set_resources = pci_dev_set_resources,
238 .enable_resources = pci_dev_enable_resources,
239 .init = ac97_audio_init,
240 .enable = i82801gx_enable,
241 .ops_pci = &pci_dev_ops_pci,
244 static struct device_operations ac97_modem_ops = {
245 .read_resources = pci_dev_read_resources,
246 .set_resources = pci_dev_set_resources,
247 .enable_resources = pci_dev_enable_resources,
248 .init = ac97_modem_init,
249 .enable = i82801gx_enable,
250 .ops_pci = &pci_dev_ops_pci,
253 /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
254 /* Note: 82801GU (ICH7-U) doesn't have AC97 audio. */
255 static const struct pci_driver i82801gx_ac97_audio __pci_driver = {
256 .ops = &ac97_audio_ops,
257 .vendor = PCI_VID_INTEL,
258 .device = 0x27de,
261 /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
262 /* Note: 82801GU (ICH7-U) doesn't have AC97 modem. */
263 static const struct pci_driver i82801gx_ac97_modem __pci_driver = {
264 .ops = &ac97_modem_ops,
265 .vendor = PCI_VID_INTEL,
266 .device = 0x27dd,