src/southbridge/intel/i82801gx/ide.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ops.h>
   7 #include <device/pci_ids.h>
   8 #include "chip.h"
   9 #include "i82801gx.h"
  10
  11 static void ide_init(struct device *dev)
  12 {
  13         u16 ideTimingConfig;
  14         u32 reg32;
  15         u32 enable_primary, enable_secondary;
  16
  17         /* Get the chip configuration */
  18         const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
  19
  20         printk(BIOS_DEBUG, "i82801gx_ide: initializing...");
  21         if (config == nullptr) {
  22                 printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in devicetree.cb!\n");
  23                 // Trying to set somewhat safe defaults instead of bailing out.
  24                 enable_primary = enable_secondary = 1;
  25         } else {
  26                 enable_primary = config->ide_enable_primary;
  27                 enable_secondary = config->ide_enable_secondary;
  28         }
  29
  30         pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER);
  31
  32         /* Native Capable, but not enabled. */
  33         pci_write_config8(dev, 0x09, 0x8a);
  34
  35         ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
  36         ideTimingConfig &= ~IDE_DECODE_ENABLE;
  37         ideTimingConfig |= IDE_SITRE;
  38         if (enable_primary) {
  39                 /* Enable primary IDE interface. */
  40                 ideTimingConfig |= IDE_DECODE_ENABLE;
  41                 ideTimingConfig |= IDE_ISP_3_CLOCKS;
  42                 ideTimingConfig |= IDE_RCT_1_CLOCKS;
  43                 ideTimingConfig |= IDE_IE0;
  44                 ideTimingConfig |= IDE_TIME0; // TIME0
  45                 printk(BIOS_DEBUG, " IDE0");
  46         }
  47         pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
  48
  49         ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
  50         ideTimingConfig &= ~IDE_DECODE_ENABLE;
  51         ideTimingConfig |= IDE_SITRE;
  52         if (enable_secondary) {
  53                 /* Enable secondary IDE interface. */
  54                 ideTimingConfig |= IDE_DECODE_ENABLE;
  55                 ideTimingConfig |= IDE_ISP_3_CLOCKS;
  56                 ideTimingConfig |= IDE_RCT_1_CLOCKS;
  57                 ideTimingConfig |= IDE_IE0;
  58                 ideTimingConfig |= IDE_TIME0;
  59                 printk(BIOS_DEBUG, " IDE1");
  60         }
  61         pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
  62
  63         /* Set IDE I/O Configuration */
  64         reg32 = 0;
  65         /* FIXME: only set FAST_* for ata/100, only ?CBx for ata/66 */
  66         if (enable_primary)
  67                 reg32 |= SIG_MODE_PRI_NORMAL | FAST_PCB0 | PCB0 | FAST_PCB1 | PCB1;
  68         if (enable_secondary)
  69                 reg32 |= SIG_MODE_SEC_NORMAL | FAST_SCB0 | SCB0 | FAST_SCB1 | SCB1;
  70         pci_write_config32(dev, IDE_CONFIG, reg32);
  71
  72         /* Set Interrupt Line */
  73         /* Interrupt Pin is set by D31IP.PIP */
  74         pci_write_config32(dev, INTR_LN, 0xff); /* Int 15 */
  75
  76         printk(BIOS_DEBUG, "\n");
  77 }
  78
  79 static struct device_operations ide_ops = {
  80         .read_resources         = pci_dev_read_resources,
  81         .set_resources          = pci_dev_set_resources,
  82         .enable_resources       = pci_dev_enable_resources,
  83         .init                   = ide_init,
  84         .enable                 = i82801gx_enable,
  85         .ops_pci                = &pci_dev_ops_pci,
  86 };
  87
  88 /* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
  89 static const struct pci_driver i82801gx_ide __pci_driver = {
  90         .ops    = &ide_ops,
  91         .vendor = PCI_VID_INTEL,
  92         .device = 0x27df,
  93 };