src/southbridge/intel/i82801gx/lpc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <cpu/intel/speedstep.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <device/pci.h>
   7 #include <device/pci_ids.h>
   8 #include <option.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <pc80/isa-dma.h>
  11 #include <pc80/i8259.h>
  12 #include <arch/io.h>
  13 #include <device/pci_ops.h>
  14 #include <arch/ioapic.h>
  15 #include <acpi/acpi.h>
  16 #include <cpu/x86/smm.h>
  17 #include <acpi/acpigen.h>
  18 #include <arch/smp/mpspec.h>
  19 #include <southbridge/intel/common/acpi_pirq_gen.h>
  20 #include <southbridge/intel/common/rcba_pirq.h>
  21 #include <southbridge/intel/common/hpet.h>
  22 #include <southbridge/intel/common/pmbase.h>
  23 #include <southbridge/intel/common/spi.h>
  24
  25 #include "chip.h"
  26 #include "i82801gx.h"
  27
  28 #define NMI_OFF 0
  29
  30 /**
  31  * Set miscellaneous static southbridge features.
  32  *
  33  * @param dev PCI device with I/O APIC control registers
  34  */
  35 static void i82801gx_enable_ioapic(struct device *dev)
  36 {
  37         register_new_ioapic_gsi0(IO_APIC_ADDR);
  38 }
  39
  40 static void i82801gx_enable_serial_irqs(struct device *dev)
  41 {
  42         /* Set packet length and toggle silent mode bit for one frame. */
  43         pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
  44 }
  45
  46 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  47  * 0x00 - 0000 = Reserved
  48  * 0x01 - 0001 = Reserved
  49  * 0x02 - 0010 = Reserved
  50  * 0x03 - 0011 = IRQ3
  51  * 0x04 - 0100 = IRQ4
  52  * 0x05 - 0101 = IRQ5
  53  * 0x06 - 0110 = IRQ6
  54  * 0x07 - 0111 = IRQ7
  55  * 0x08 - 1000 = Reserved
  56  * 0x09 - 1001 = IRQ9
  57  * 0x0A - 1010 = IRQ10
  58  * 0x0B - 1011 = IRQ11
  59  * 0x0C - 1100 = IRQ12
  60  * 0x0D - 1101 = Reserved
  61  * 0x0E - 1110 = IRQ14
  62  * 0x0F - 1111 = IRQ15
  63  * PIRQ[n]_ROUT[7] - PIRQ Routing Control
  64  * 0x80 - The PIRQ is not routed.
  65  */
  66
  67 static void i82801gx_pirq_init(struct device *dev)
  68 {
  69         struct device *irq_dev;
  70         /* Get the chip configuration */
  71         const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
  72
  73         pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
  74         pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
  75         pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
  76         pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
  77
  78         pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
  79         pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
  80         pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
  81         pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
  82
  83         /* Eric Biederman once said we should let the OS do this.
  84          * I am not so sure anymore he was right.
  85          */
  86
  87         for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
  88                 u8 int_pin = 0, int_line = 0;
  89
  90                 if (!is_enabled_pci(irq_dev))
  91                         continue;
  92
  93                 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
  94
  95                 switch (int_pin) {
  96                 case 1:
  97                         /* INTA# */ int_line = config->pirqa_routing; break;
  98                 case 2:
  99                         /* INTB# */ int_line = config->pirqb_routing; break;
 100                 case 3:
 101                         /* INTC# */ int_line = config->pirqc_routing; break;
 102                 case 4:
 103                         /* INTD# */ int_line = config->pirqd_routing; break;
 104                 }
 105
 106                 if (!int_line)
 107                         continue;
 108
 109                 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
 110         }
 111 }
 112
 113 static void i82801gx_gpi_routing(struct device *dev)
 114 {
 115         /* Get the chip configuration */
 116         const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
 117         u32 reg32 = 0;
 118
 119         /* An array would be much nicer here, or some other method of doing this. */
 120         reg32 |= (config->gpi0_routing & 0x03) << 0;
 121         reg32 |= (config->gpi1_routing & 0x03) << 2;
 122         reg32 |= (config->gpi2_routing & 0x03) << 4;
 123         reg32 |= (config->gpi3_routing & 0x03) << 6;
 124         reg32 |= (config->gpi4_routing & 0x03) << 8;
 125         reg32 |= (config->gpi5_routing & 0x03) << 10;
 126         reg32 |= (config->gpi6_routing & 0x03) << 12;
 127         reg32 |= (config->gpi7_routing & 0x03) << 14;
 128         reg32 |= (config->gpi8_routing & 0x03) << 16;
 129         reg32 |= (config->gpi9_routing & 0x03) << 18;
 130         reg32 |= (config->gpi10_routing & 0x03) << 20;
 131         reg32 |= (config->gpi11_routing & 0x03) << 22;
 132         reg32 |= (config->gpi12_routing & 0x03) << 24;
 133         reg32 |= (config->gpi13_routing & 0x03) << 26;
 134         reg32 |= (config->gpi14_routing & 0x03) << 28;
 135         reg32 |= (config->gpi15_routing & 0x03) << 30;
 136
 137         pci_write_config32(dev, GPIO_ROUT, reg32);
 138 }
 139
 140 static void i82801gx_power_options(struct device *dev)
 141 {
 142         u8 reg8;
 143         u16 reg16;
 144         u32 reg32;
 145         const char *state;
 146         /* Get the chip configuration */
 147         const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
 148
 149         /* Which state do we want to goto after g3 (power restored)?
 150          * 0 == S0 Full On
 151          * 1 == S5 Soft Off
 152          *
 153          * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
 154          */
 155         const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
 156
 157         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 158         reg8 &= 0xfe;
 159         switch (pwr_on) {
 160         case MAINBOARD_POWER_OFF:
 161                 reg8 |= 1;
 162                 state = "off";
 163                 break;
 164         case MAINBOARD_POWER_ON:
 165                 reg8 &= ~1;
 166                 state = "on";
 167                 break;
 168         case MAINBOARD_POWER_KEEP:
 169                 reg8 &= ~1;
 170                 state = "state keep";
 171                 break;
 172         default:
 173                 state = "undefined";
 174         }
 175
 176         reg8 |= (3 << 4);       /* avoid #S4 assertions */
 177         reg8 &= ~(1 << 3);      /* minimum assertion is 1 to 2 RTCCLK */
 178
 179         pci_write_config8(dev, GEN_PMCON_3, reg8);
 180         printk(BIOS_INFO, "Set power %s after power failure.\n", state);
 181
 182         /* Set up NMI on errors. */
 183         reg8 = inb(0x61);
 184         reg8 &= 0x0f;           /* Higher Nibble must be 0 */
 185         reg8 &= ~(1 << 3);      /* IOCHK# NMI Enable */
 186         // reg8 &= ~(1 << 2);   /* PCI SERR# Enable */
 187         reg8 |= (1 << 2); /* PCI SERR# Disable for now */
 188         outb(reg8, 0x61);
 189
 190         reg8 = inb(0x70);
 191         const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
 192         if (nmi_option) {
 193                 printk(BIOS_INFO, "NMI sources enabled.\n");
 194                 reg8 &= ~(1 << 7);      /* Set NMI. */
 195         } else {
 196                 printk(BIOS_INFO, "NMI sources disabled.\n");
 197                 reg8 |= (1 << 7);       /* Can't mask NMI from PCI-E and NMI_NOW */
 198         }
 199         outb(reg8, 0x70);
 200
 201         /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
 202         reg16 = pci_read_config16(dev, GEN_PMCON_1);
 203         reg16 &= ~(3 << 0);     // SMI# rate 1 minute
 204         reg16 |= (1 << 2);      // CLKRUN_EN - Mobile/Ultra only
 205         reg16 |= (1 << 3);      // Speedstep Enable - Mobile/Ultra only
 206         reg16 |= (1 << 5);      // CPUSLP_EN Desktop only
 207
 208         if (config->c4onc3_enable)
 209                 reg16 |= (1 << 7);
 210
 211         // another laptop wants this?
 212         // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
 213         reg16 |= (1 << 10);     // BIOS_PCI_EXP_EN - Desktop/Mobile only
 214         if (CONFIG(DEBUG_PERIODIC_SMI))
 215                 reg16 |= (3 << 0); // Periodic SMI every 8s
 216         pci_write_config16(dev, GEN_PMCON_1, reg16);
 217
 218         // Set the board's GPI routing.
 219         i82801gx_gpi_routing(dev);
 220
 221         write_pmbase32(GPE0_EN, config->gpe0_en);
 222         write_pmbase16(ALT_GP_SMI_EN, config->alt_gp_smi_en);
 223
 224         /* Set up power management block and determine sleep mode */
 225         reg32 = read_pmbase32(PM1_CNT);
 226
 227         reg32 &= ~(7 << 10);    // SLP_TYP
 228         reg32 |= (1 << 1);      // enable C3->C0 transition on bus master
 229         reg32 |= (1 << 0);      // SCI_EN
 230         write_pmbase32(PM1_CNT, reg32);
 231 }
 232
 233 static void i82801gx_configure_cstates(struct device *dev)
 234 {
 235         // Enable Popup & Popdown
 236         pci_or_config8(dev, 0xa9, (1 << 4) | (1 << 3) | (1 << 2));
 237
 238         // Set Deeper Sleep configuration to recommended values
 239         // Deeper Sleep to Stop CPU: 34-40us
 240         // Deeper Sleep to Sleep: 15us
 241         pci_update_config8(dev, 0xaa, 0xf0, (2 << 2) | (2 << 0));
 242 }
 243
 244 static void i82801gx_rtc_init(struct device *dev)
 245 {
 246         u8 reg8;
 247         int rtc_failed;
 248
 249         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 250         rtc_failed = reg8 & RTC_BATTERY_DEAD;
 251         if (rtc_failed) {
 252                 reg8 &= ~RTC_BATTERY_DEAD;
 253                 pci_write_config8(dev, GEN_PMCON_3, reg8);
 254         }
 255         printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 256
 257         cmos_init(rtc_failed);
 258 }
 259
 260 static void enable_clock_gating(void)
 261 {
 262         u32 reg32;
 263
 264         /* Enable Clock Gating for most devices */
 265         reg32 = RCBA32(CG);
 266         reg32 |= (1 << 31);     // LPC clock gating
 267         reg32 |= (1 << 30);     // PATA clock gating
 268         // SATA clock gating
 269         reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
 270         reg32 |= (1 << 23);     // AC97 clock gating
 271         reg32 |= (1 << 19);     // USB EHCI clock gating
 272         reg32 |= (1 << 3) | (1 << 1);   // DMI clock gating
 273         reg32 |= (1 << 2);      // PCIe clock gating;
 274         reg32 &= ~(1 << 20); // No static clock gating for USB
 275         reg32 &= ~((1 << 29) | (1 << 28)); // Disable UHCI clock gating
 276         RCBA32(CG) = reg32;
 277 }
 278
 279 static void i82801gx_set_acpi_mode(struct device *dev)
 280 {
 281         if (!acpi_is_wakeup_s3()) {
 282                 apm_control(APM_CNT_ACPI_DISABLE);
 283         } else {
 284                 apm_control(APM_CNT_ACPI_ENABLE);
 285         }
 286 }
 287
 288 static void i82801gx_spi_init(void)
 289 {
 290         u16 spicontrol;
 291
 292         spicontrol = RCBA16(SPIBASE + 2);
 293         spicontrol &= ~(1 << 0); // SPI Access Request
 294         RCBA16(SPIBASE + 2) = spicontrol;
 295 }
 296
 297 static void i82801gx_fixups(struct device *dev)
 298 {
 299         /* This needs to happen after PCI enumeration */
 300         RCBA32(0x1d40) |= 1;
 301
 302         /* USB Transient Disconnect Detect:
 303          * Prevent a SE0 condition on the USB ports from being
 304          * interpreted by the UHCI controller as a disconnect
 305          */
 306         pci_write_config8(dev, 0xad, 0x3);
 307 }
 308
 309 static void lpc_init(struct device *dev)
 310 {
 311         printk(BIOS_DEBUG, "i82801gx: %s\n", __func__);
 312
 313         /* IO APIC initialization. */
 314         i82801gx_enable_ioapic(dev);
 315
 316         i82801gx_enable_serial_irqs(dev);
 317
 318         /* Setup the PIRQ. */
 319         i82801gx_pirq_init(dev);
 320
 321         /* Setup power options. */
 322         i82801gx_power_options(dev);
 323
 324         /* Configure Cx state registers */
 325         i82801gx_configure_cstates(dev);
 326
 327         /* Initialize the real time clock. */
 328         i82801gx_rtc_init(dev);
 329
 330         /* Initialize ISA DMA. */
 331         isa_dma_init();
 332
 333         /* Initialize the High Precision Event Timers, if present. */
 334         enable_hpet();
 335
 336         /* Initialize Clock Gating */
 337         enable_clock_gating();
 338
 339         setup_i8259();
 340
 341         /* The OS should do this? */
 342         /* Interrupt 9 should be level triggered (SCI) */
 343         i8259_configure_irq_trigger(9, 1);
 344
 345         i82801gx_set_acpi_mode(dev);
 346
 347         i82801gx_spi_init();
 348
 349         i82801gx_fixups(dev);
 350 }
 351
 352 static void i82801gx_lpc_read_resources(struct device *dev)
 353 {
 354         struct resource *res;
 355         u8 io_index = 0;
 356         int i;
 357
 358         /* Get the normal PCI resources of this device. */
 359         pci_dev_read_resources(dev);
 360
 361         /* Add an extra subtractive resource for both memory and I/O. */
 362         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 363         res->base = 0;
 364         res->size = 0x1000;
 365         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 366                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 367
 368         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 369         res->base = 0xff800000;
 370         res->size = 0x00800000; /* 8 MB for flash */
 371         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 372                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 373
 374         res = new_resource(dev, 3); /* IOAPIC */
 375         res->base = IO_APIC_ADDR;
 376         res->size = 0x00001000;
 377         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 378
 379         /* Set IO decode ranges if required.*/
 380         for (i = 0; i < 4; i++) {
 381                 u32 gen_dec;
 382                 gen_dec = pci_read_config32(dev, 0x84 + 4 * i);
 383
 384                 if ((gen_dec & 0xFFFC) > 0x1000) {
 385                         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 386                         res->base = gen_dec & 0xFFFC;
 387                         res->size = (gen_dec >> 16) & 0xFC;
 388                         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 389                                 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 390                 }
 391         }
 392 }
 393
 394 static void lpc_final(struct device *dev)
 395 {
 396         u16 tco1_cnt;
 397
 398         if (!CONFIG(INTEL_CHIPSET_LOCKDOWN))
 399                 return;
 400
 401         if (CONFIG(BOOT_DEVICE_SPI_FLASH))
 402                 spi_finalize_ops();
 403
 404         /* Lock SPIBAR */
 405         SPIBAR16(0) = SPIBAR16(0) | (1 << 15);
 406
 407         /* BIOS Interface Lockdown */
 408         RCBA32(0x3410) |= 1 << 0;
 409
 410         /* Global SMI Lock */
 411         pci_or_config16(dev, GEN_PMCON_1, 1 << 4);
 412
 413         /* TCO_Lock */
 414         tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT);
 415         tco1_cnt |= (1 << 12); /* TCO lock */
 416         outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT);
 417
 418         /* Indicate finalize step with post code */
 419         post_code(POSTCODE_OS_BOOT);
 420 }
 421
 422 static const char *lpc_acpi_name(const struct device *dev)
 423 {
 424         return "LPCB";
 425 }
 426
 427 static void southbridge_fill_ssdt(const struct device *device)
 428 {
 429         intel_acpi_gen_def_acpi_pirq(device);
 430 }
 431
 432 static struct device_operations device_ops = {
 433         .read_resources         = i82801gx_lpc_read_resources,
 434         .set_resources          = pci_dev_set_resources,
 435         .enable_resources       = pci_dev_enable_resources,
 436         .write_acpi_tables      = acpi_write_hpet,
 437         .acpi_fill_ssdt         = southbridge_fill_ssdt,
 438         .acpi_name              = lpc_acpi_name,
 439         .init                   = lpc_init,
 440         .scan_bus               = scan_static_bus,
 441         .enable                 = i82801gx_enable,
 442         .ops_pci                = &pci_dev_ops_pci,
 443         .final                  = lpc_final,
 444 };
 445
 446 static const unsigned short pci_device_ids[] = {
 447         0x27b0, /* 82801GH (ICH7 DH) */
 448         0x27b8, /* 82801GB/GR (ICH7/ICH7R) */
 449         0x27b9, /* 82801GBM/GU (ICH7-M/ICH7-U) */
 450         0x27bc, /* 82NM10 (NM10) */
 451         0x27bd, /* 82801GHM (ICH7-M DH) */
 452         0
 453 };
 454
 455 static const struct pci_driver ich7_lpc __pci_driver = {
 456         .ops    = &device_ops,
 457         .vendor = PCI_VID_INTEL,
 458         .devices = pci_device_ids,
 459 };
 460
 461 bool southbridge_support_c5(void)
 462 {
 463         return false;
 464 }
 465
 466 bool southbridge_support_c6(void)
 467 {
 468         return false;
 469 }