mb/google/nissa/var/rull: add ssd timing and modify ssd GPIO pins of rtd3
[coreboot2.git] / src / southbridge / intel / i82801ix / Makefile.mk
blob8db30ad64ac8efa10c60625b660042f4304edc65
1 ## SPDX-License-Identifier: GPL-2.0-only
3 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y)
5 bootblock-y += bootblock.c
6 bootblock-y += early_init.c
8 romstage-y += dmi_setup.c
9 romstage-y += early_init.c
11 ramstage-y += azalia.c
12 ramstage-y += fadt.c
13 ramstage-y += i82801ix.c
14 ramstage-y += lpc.c
15 ramstage-y += pci.c
16 ramstage-y += pcie.c
17 ramstage-y += sata.c
18 ramstage-y += smbus.c
19 ramstage-y += thermal.c
20 ramstage-y += usb_ehci.c
21 ramstage-y += ../common/pciehp.c
23 smm-y += smihandler.c
25 CPPFLAGS_common += -I$(src)/southbridge/intel/i82801ix/include
27 endif